{"L1_003": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier matmul problems (wrong results or slower than eager)\n- Pitfall: When using split-K, keep the split count small; a very large split writes and re-reads a huge partial-sum buffer plus an extra reduction launch, eating the occupancy gain.\n- Pitfall: Strict fp32 Triton tl.dot (allow_tf32=False) rarely beats cuBLAS on matmul; a hand split-K version was correct but still 0.88x. Fuse surrounding ops or exploit structure instead of reimplementing plain GEMM.\n- Pitfall: For bandwidth-bound Triton kernels, give each program more work: larger tiles, multiple rows per program, more warps. Tiny per-program work and Python launch overhead lose to cuBLAS/ATen kernels.\n- Pitfall: Don't expect a single-pass memory-bound elementwise or broadcast kernel to beat eager, which already runs near bandwidth peak. Win by fusing multiple ops or reducing memory traffic.\n- Pitfall: If writing a Triton GEMM anyway, use @triton.autotune over several BM/BN/BK, num_warps and num_stages configs, plus grouped tile ordering. A single fixed 64x64x32 config is far slower than eager.\n- Pitfall: Do not hand-write a plain fp32 matmul with TF32 disabled; it loses to cuBLAS. Call torch.matmul on transposed views (no .contiguous copies) and spend custom-kernel effort only on fusing surrounding ops.\n\n### Verified recipes for matmul problems (speedups measured by the protected evaluator)\n- [36.02x on Gemm_Subtract_GlobalAvgPool_LogSumExp_GELU_ResidualAdd] Look for algebraic collapse before writing kernels. When a GEMM feeds a linear reduction (a mean or sum over output features), rewrite mean(Wx+b-s) as x\u00b7(W.sum(0)/N) + mean(b-s). This turns the GEMM into a GEMV kept in torch/cuBLAS. Check for degenerate ops: logsumexp over a size-1 dim is the identity, so drop it. Apply cheap scalar ops such as GELU on the reduced vector in torch. Fuse the final per-row broadcast plus residual add into one coalesced 1D Triton elementwise kernel (BLOCK=1024, row = offs // n_feat). fp32 summation stays within 1e-4.\n- [4.58x on Matmul_for_lower_triangular_matrices] Exploit structural sparsity (triangular, banded, diagonal) with a custom Triton tiled matmul instead of dense cuBLAS. Use a 2D grid of output tiles and return early for tiles that are entirely zero. Clamp the K-loop to the nonzero range: for tril\u00d7tril, run from floor(n_lo/BK)*BK to min(m_lo+BM, N). Accumulate in fp32 with tl.dot(allow_tf32=False) to stay within 1e-4. Apply the output mask with tl.where before the store. Pre-zero the output with torch.zeros so skipped tiles stay zero. 64x64x32 tiles, 4 warps, 3 stages.\n- [4.11x on Matmul_for_upper_triangular_matrices] Exploit structural sparsity (triangular, banded, or block-sparse) with a Triton tiled GEMM instead of dense cuBLAS. Use a 2D grid over output tiles, early-return tiles that are entirely masked out, and clip the K loop to the nonzero range (for triu\u00b7triu, k from the row-tile start to the column-tile end, aligned to BLOCK_K). Accumulate in fp32 with tl.dot(allow_tf32=False) to stay within 1e-4. Apply the triangle mask with tl.where before storing. Preallocate the output with torch.zeros so skipped tiles stay zero. Tiles 64x64x32, 4 warps, 3 stages.\n- [1.02x on Matmul_BatchNorm_BiasAdd_Divide_Swish] Keep the GEMM (nn.Linear) in cuBLAS via torch and fuse only the epilogue in Triton. For training-mode BatchNorm, run a per-column stats kernel that accumulates sum and sum-of-squares in fp32, giving biased variance for normalization. Update running_mean/var under no_grad using the unbiased var, M/(M-1). Then one flat elementwise kernel applies normalize, gamma/beta, bias, divide and Swish, indexing per-column params with offs % N. Gains are small because the GEMM dominates; next, coalesce stats loads with 2D column tiles.\n- [1.01x on Matmul_GroupNorm_LeakyReLU_Sum] Keep the Linear GEMM in cuBLAS via the module's own fc (F.linear with bias). Fuse every downstream per-row op into one Triton kernel reading the GEMM output once: GroupNorm, affine, LeakyReLU and x+x (as y*2). Use one program per (row, group), BLOCK=next_power_of_2(group size), contiguous masked loads. Compute the two-pass mean/variance in fp32 registers and mask padded lanes before squaring. Expect small gains, since the GEMM dominates; for tiny groups, batch several groups per program to cut launch and occupancy waste.\n- [1.01x on Gemm_Sigmoid_Scaling_ResidualAdd] Keep the GEMM in cuBLAS through nn.Linear / F.linear in fp32, with the bias folded in by cuBLAS. Replace the chain of eager elementwise ops (sigmoid, scale, residual add) with a single flat 1D Triton kernel: one load, compute s=1/(1+exp(-v)), y=s*scale+v, one store. Use contiguous masked blocks of 1024 and grid=cdiv(n,BLOCK). Writing in place into the GEMM output saves an allocation. The gain is small because the GEMM dominates; a bigger win requires a fused-epilogue GEMM.\n\n### A verified kernel for a related matmul problem (L2_051 Gemm_Subtract_GlobalAvgPool_LogSumExp_GELU_ResidualAdd, 36.02x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef add_kernel(x_ptr, s_ptr, out_ptr, n_feat, n, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < n\n row = offs // n_feat\n v = tl.load(x_ptr + offs, mask=mask)\n s = tl.load(s_ptr + row, mask=mask)\n tl.store(out_ptr + offs, v + s, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_features, out_features, bias=True):\n super().__init__()\n self.gemm = nn.Linear(in_features, out_features, bias=bias)\n self.subtract = nn.Parameter(torch.randn(out_features))\n self.out_features = out_features\n\n def forward(self, x):\n # mean over output features of (Wx + b - subtract) = (colsum/out)\u00b7x + c\n colsum = self.gemm.weight.sum(dim=0) / self.out_features # (in,)\n if self.gemm.bias is not None:\n c = (self.gemm.bias - self.subtract).mean()\n else:\n c = (-self.subtract).mean()\n s = x @ colsum + c # (batch,)\n # logsumexp over single element (dim=1 after keepdim mean) is identity\n s = F.gelu(s)\n out = torch.empty_like(x)\n n = x.numel()\n n_feat = x.shape[1]\n BLOCK = 1024\n grid = (triton.cdiv(n, BLOCK),)\n add_kernel[grid](x, s, out, n_feat, n, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related matmul problem (L1_015 Matmul_for_lower_triangular_matrices, 4.58x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n@triton.jit\ndef tril_mm_kernel(A_ptr, B_ptr, C_ptr, N,\n BLOCK_M: tl.constexpr, BLOCK_N: tl.constexpr, BLOCK_K: tl.constexpr):\n pid_m = tl.program_id(0)\n pid_n = tl.program_id(1)\n\n m_lo = pid_m * BLOCK_M\n n_lo = pid_n * BLOCK_N\n\n if n_lo > (m_lo + BLOCK_M - 1):\n return\n\n offs_m = m_lo + tl.arange(0, BLOCK_M)\n offs_n = n_lo + tl.arange(0, BLOCK_N)\n offs_k = tl.arange(0, BLOCK_K)\n\n acc = tl.zeros((BLOCK_M, BLOCK_N), dtype=tl.float32)\n\n k_start = (n_lo // BLOCK_K) * BLOCK_K\n k_end = tl.minimum(m_lo + BLOCK_M, N)\n\n k = k_start\n while k < k_end:\n kk = k + offs_k\n a = tl.load(A_ptr + offs_m[:, None] * N + kk[None, :],\n mask=(offs_m[:, None] < N) & (kk[None, :] < N), other=0.0)\n b = tl.load(B_ptr + kk[:, None] * N + offs_n[None, :],\n mask=(kk[:, None] < N) & (offs_n[None, :] < N), other=0.0)\n acc += tl.dot(a, b, allow_tf32=False)\n k += BLOCK_K\n\n mask_tri = offs_m[:, None] >= offs_n[None, :]\n acc = tl.where(mask_tri, acc, 0.0)\n store_mask = (offs_m[:, None] < N) & (offs_n[None, :] < N)\n tl.store(C_ptr + offs_m[:, None] * N + offs_n[None, :], acc, mask=store_mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self):\n super().__init__()\n\n def forward(self, A, B):\n A = A.contiguous()\n B = B.contiguous()\n N = A.shape[0]\n C = torch.zeros_like(A)\n BLOCK_M = 64\n BLOCK_N = 64\n BLOCK_K = 32\n grid = (triton.cdiv(N, BLOCK_M), triton.cdiv(N, BLOCK_N))\n tril_mm_kernel[grid](A, B, C, N, BLOCK_M=BLOCK_M, BLOCK_N=BLOCK_N, BLOCK_K=BLOCK_K,\n num_warps=4, num_stages=3)\n return C\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier matmul problems (wrong results or slower than eager)\n- Pitfall: When using split-K, keep the split count small; a very large split writes and re-reads a huge partial-sum buffer plus an extra reduction launch, eating the occupancy gain.\n- Pitfall: Strict fp32 Triton tl.dot (allow_tf32=False) rarely beats cuBLAS on matmul; a hand split-K version was correct but still 0.88x. Fuse surrounding ops or exploit structure instead of reimplementing plain GEMM.\n- Pitfall: For bandwidth-bound Triton kernels, give each program more work: larger tiles, multiple rows per program, more warps. Tiny per-program work and Python launch overhead lose to cuBLAS/ATen kernels.\n- Pitfall: Don't expect a single-pass memory-bound elementwise or broadcast kernel to beat eager, which already runs near bandwidth peak. Win by fusing multiple ops or reducing memory traffic.\n- Pitfall: If writing a Triton GEMM anyway, use @triton.autotune over several BM/BN/BK, num_warps and num_stages configs, plus grouped tile ordering. A single fixed 64x64x32 config is far slower than eager.\n- Pitfall: Do not hand-write a plain fp32 matmul with TF32 disabled; it loses to cuBLAS. Call torch.matmul on transposed views (no .contiguous copies) and spend custom-kernel effort only on fusing surrounding ops.\n\n### Verified recipes for matmul problems (speedups measured by the protected evaluator)\n- [36.02x on Gemm_Subtract_GlobalAvgPool_LogSumExp_GELU_ResidualAdd] Look for algebraic collapse before writing kernels. When a GEMM feeds a linear reduction (a mean or sum over output features), rewrite mean(Wx+b-s) as x\u00b7(W.sum(0)/N) + mean(b-s). This turns the GEMM into a GEMV kept in torch/cuBLAS. Check for degenerate ops: logsumexp over a size-1 dim is the identity, so drop it. Apply cheap scalar ops such as GELU on the reduced vector in torch. Fuse the final per-row broadcast plus residual add into one coalesced 1D Triton elementwise kernel (BLOCK=1024, row = offs // n_feat). fp32 summation stays within 1e-4.\n- [4.58x on Matmul_for_lower_triangular_matrices] Exploit structural sparsity (triangular, banded, diagonal) with a custom Triton tiled matmul instead of dense cuBLAS. Use a 2D grid of output tiles and return early for tiles that are entirely zero. Clamp the K-loop to the nonzero range: for tril\u00d7tril, run from floor(n_lo/BK)*BK to min(m_lo+BM, N). Accumulate in fp32 with tl.dot(allow_tf32=False) to stay within 1e-4. Apply the output mask with tl.where before the store. Pre-zero the output with torch.zeros so skipped tiles stay zero. 64x64x32 tiles, 4 warps, 3 stages.\n- [4.11x on Matmul_for_upper_triangular_matrices] Exploit structural sparsity (triangular, banded, or block-sparse) with a Triton tiled GEMM instead of dense cuBLAS. Use a 2D grid over output tiles, early-return tiles that are entirely masked out, and clip the K loop to the nonzero range (for triu\u00b7triu, k from the row-tile start to the column-tile end, aligned to BLOCK_K). Accumulate in fp32 with tl.dot(allow_tf32=False) to stay within 1e-4. Apply the triangle mask with tl.where before storing. Preallocate the output with torch.zeros so skipped tiles stay zero. Tiles 64x64x32, 4 warps, 3 stages.\n- [1.02x on Matmul_BatchNorm_BiasAdd_Divide_Swish] Keep the GEMM (nn.Linear) in cuBLAS via torch and fuse only the epilogue in Triton. For training-mode BatchNorm, run a per-column stats kernel that accumulates sum and sum-of-squares in fp32, giving biased variance for normalization. Update running_mean/var under no_grad using the unbiased var, M/(M-1). Then one flat elementwise kernel applies normalize, gamma/beta, bias, divide and Swish, indexing per-column params with offs % N. Gains are small because the GEMM dominates; next, coalesce stats loads with 2D column tiles.\n- [1.01x on Matmul_GroupNorm_LeakyReLU_Sum] Keep the Linear GEMM in cuBLAS via the module's own fc (F.linear with bias). Fuse every downstream per-row op into one Triton kernel reading the GEMM output once: GroupNorm, affine, LeakyReLU and x+x (as y*2). Use one program per (row, group), BLOCK=next_power_of_2(group size), contiguous masked loads. Compute the two-pass mean/variance in fp32 registers and mask padded lanes before squaring. Expect small gains, since the GEMM dominates; for tiny groups, batch several groups per program to cut launch and occupancy waste.\n- [1.01x on Gemm_Sigmoid_Scaling_ResidualAdd] Keep the GEMM in cuBLAS through nn.Linear / F.linear in fp32, with the bias folded in by cuBLAS. Replace the chain of eager elementwise ops (sigmoid, scale, residual add) with a single flat 1D Triton kernel: one load, compute s=1/(1+exp(-v)), y=s*scale+v, one store. Use contiguous masked blocks of 1024 and grid=cdiv(n,BLOCK). Writing in place into the GEMM output saves an allocation. The gain is small because the GEMM dominates; a bigger win requires a fused-epilogue GEMM.\n\n### A verified kernel for a related matmul problem (L2_051 Gemm_Subtract_GlobalAvgPool_LogSumExp_GELU_ResidualAdd, 36.02x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef add_kernel(x_ptr, s_ptr, out_ptr, n_feat, n, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < n\n row = offs // n_feat\n v = tl.load(x_ptr + offs, mask=mask)\n s = tl.load(s_ptr + row, mask=mask)\n tl.store(out_ptr + offs, v + s, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_features, out_features, bias=True):\n super().__init__()\n self.gemm = nn.Linear(in_features, out_features, bias=bias)\n self.subtract = nn.Parameter(torch.randn(out_features))\n self.out_features = out_features\n\n def forward(self, x):\n # mean over output features of (Wx + b - subtract) = (colsum/out)\u00b7x + c\n colsum = self.gemm.weight.sum(dim=0) / self.out_features # (in,)\n if self.gemm.bias is not None:\n c = (self.gemm.bias - self.subtract).mean()\n else:\n c = (-self.subtract).mean()\n s = x @ colsum + c # (batch,)\n # logsumexp over single element (dim=1 after keepdim mean) is identity\n s = F.gelu(s)\n out = torch.empty_like(x)\n n = x.numel()\n n_feat = x.shape[1]\n BLOCK = 1024\n grid = (triton.cdiv(n, BLOCK),)\n add_kernel[grid](x, s, out, n_feat, n, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related matmul problem (L1_015 Matmul_for_lower_triangular_matrices, 4.58x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n@triton.jit\ndef tril_mm_kernel(A_ptr, B_ptr, C_ptr, N,\n BLOCK_M: tl.constexpr, BLOCK_N: tl.constexpr, BLOCK_K: tl.constexpr):\n pid_m = tl.program_id(0)\n pid_n = tl.program_id(1)\n\n m_lo = pid_m * BLOCK_M\n n_lo = pid_n * BLOCK_N\n\n if n_lo > (m_lo + BLOCK_M - 1):\n return\n\n offs_m = m_lo + tl.arange(0, BLOCK_M)\n offs_n = n_lo + tl.arange(0, BLOCK_N)\n offs_k = tl.arange(0, BLOCK_K)\n\n acc = tl.zeros((BLOCK_M, BLOCK_N), dtype=tl.float32)\n\n k_start = (n_lo // BLOCK_K) * BLOCK_K\n k_end = tl.minimum(m_lo + BLOCK_M, N)\n\n k = k_start\n while k < k_end:\n kk = k + offs_k\n a = tl.load(A_ptr + offs_m[:, None] * N + kk[None, :],\n mask=(offs_m[:, None] < N) & (kk[None, :] < N), other=0.0)\n b = tl.load(B_ptr + kk[:, None] * N + offs_n[None, :],\n mask=(kk[:, None] < N) & (offs_n[None, :] < N), other=0.0)\n acc += tl.dot(a, b, allow_tf32=False)\n k += BLOCK_K\n\n mask_tri = offs_m[:, None] >= offs_n[None, :]\n acc = tl.where(mask_tri, acc, 0.0)\n store_mask = (offs_m[:, None] < N) & (offs_n[None, :] < N)\n tl.store(C_ptr + offs_m[:, None] * N + offs_n[None, :], acc, mask=store_mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self):\n super().__init__()\n\n def forward(self, A, B):\n A = A.contiguous()\n B = B.contiguous()\n N = A.shape[0]\n C = torch.zeros_like(A)\n BLOCK_M = 64\n BLOCK_N = 64\n BLOCK_K = 32\n grid = (triton.cdiv(N, BLOCK_M), triton.cdiv(N, BLOCK_N))\n tril_mm_kernel[grid](A, B, C, N, BLOCK_M=BLOCK_M, BLOCK_N=BLOCK_N, BLOCK_K=BLOCK_K,\n num_warps=4, num_stages=3)\n return C\n```"}, "same_for_readers": true, "ctx_chars": 10384, "ctx_sha": "4573cb1c62d0cdf8", "names_self": false, "family": "matmul", "level": 1, "name": "Batched_matrix_multiplication", "instruction": "KernelBench level 1 problem L1_003 (Batched_matrix_multiplication), op family: matmul.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Performs batched matrix multiplication (C = A * B) where A, B, and C have the same batch dimension.\n \"\"\"\n def __init__(self):\n super(Model, self).__init__()\n \n def forward(self, A: torch.Tensor, B: torch.Tensor) -> torch.Tensor:\n \"\"\"\n Performs batched matrix multiplication.\n\n Args:\n A: Input tensor of shape (batch_size, m, k).\n B: Input tensor of shape (batch_size, k, n).\n\n Returns:\n C: Output tensor of shape (batch_size, m, n).\n \"\"\"\n return torch.bmm(A, B)\n\nbatch_size = 128\nm = 128 * 4\nk = 256 * 4\nn = 512 * 4\n\ndef get_inputs():\n A = torch.rand(batch_size, m, k)\n B = torch.rand(batch_size, k, n)\n return [A, B]\n\ndef get_init_inputs():\n return [] # No special initialization inputs needed```\n"}, "L1_054": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L1_050 conv_standard_2D__square_input__square_kernel, 1.00x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef bias_kernel(x_ptr, bias_ptr, N, C, S, TOTAL, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n c = (offs // S) % C\n b = tl.load(bias_ptr + c, mask=mask, other=0.0)\n v = tl.load(x_ptr + offs, mask=mask, other=0.0)\n tl.store(x_ptr + offs, v + b, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, num_classes=1000):\n super(ModelNew, self).__init__()\n self.conv1 = nn.Conv2d(in_channels=3, out_channels=96, kernel_size=11, stride=4, padding=2)\n\n def forward(self, x):\n out = F.conv2d(x, self.conv1.weight, None, stride=4, padding=2)\n out = out.contiguous()\n N, C, H, W = out.shape\n S = H * W\n TOTAL = N * C * S\n BLOCK = 1024\n grid = (triton.cdiv(TOTAL, BLOCK),)\n bias_kernel[grid](out, self.conv1.bias.contiguous(), N, C, S, TOTAL, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L1_083 conv_depthwise_2D_square_input_asymmetric_kernel, 2.43x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef dwconv_kernel(x_ptr, w_ptr, b_ptr, out_ptr,\n N, C, H, W, OH, OW,\n stride, padding, dilation,\n K: tl.constexpr, HAS_BIAS: tl.constexpr, BLOCK: tl.constexpr):\n pid_row = tl.program_id(0)\n pid_col = tl.program_id(1)\n\n oh = pid_row % OH\n tmp = pid_row // OH\n c = tmp % C\n n = tmp // C\n\n ow = pid_col * BLOCK + tl.arange(0, BLOCK)\n mask = ow < OW\n\n iw = ow * stride - padding\n ih0 = oh * stride - padding\n wvalid = mask & (iw >= 0) & (iw < W)\n\n acc = tl.zeros((BLOCK,), tl.float32)\n base = (n.to(tl.int64) * C + c) * H * W\n wbase = c * K\n\n for k in tl.static_range(K):\n ih = ih0 + k * dilation\n if (ih >= 0) & (ih < H):\n idx = base + ih.to(tl.int64) * W + iw\n v = tl.load(x_ptr + idx, mask=wvalid, other=0.0)\n wv = tl.load(w_ptr + wbase + k)\n acc += v * wv\n\n if HAS_BIAS:\n bv = tl.load(b_ptr + c)\n acc += bv\n\n obase = ((n.to(tl.int64) * C + c) * OH + oh) * OW\n tl.store(out_ptr + obase + ow, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, dilation: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv2d = nn.Conv2d(in_channels, in_channels, kernel_size=(kernel_size, 1),\n stride=stride, padding=padding, dilation=dilation,\n groups=in_channels, bias=bias)\n self.in_channels = in_channels\n self.kernel_size = kernel_size\n self.stride = stride\n self.padding = padding\n self.dilation = dilation\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n x = x.contiguous()\n N, C, H, W = x.shape\n K = self.kernel_size\n stride = self.stride\n padding = self.padding\n dilation = self.dilation\n OH = (H + 2 * padding - dilation * (K - 1) - 1) // stride + 1\n OW = (W + 2 * padding - 1) // stride + 1\n out = torch.empty((N, C, OH, OW), device=x.device, dtype=x.dtype)\n w = self.conv2d.weight.contiguous().view(-1)\n if self.has_bias:\n b = self.conv2d.bias.contiguous()\n else:\n b = torch.empty(1, device=x.device, dtype=x.dtype)\n BLOCK = 256\n grid = (N * C * OH, triton.cdiv(OW, BLOCK))\n dwconv_kernel[grid](x, w, b, out,\n N, C, H, W, OH, OW,\n stride, padding, dilation,\n K=K, HAS_BIAS=self.has_bias, BLOCK=BLOCK,\n num_warps=4)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L1_050 conv_standard_2D__square_input__square_kernel, 1.00x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef bias_kernel(x_ptr, bias_ptr, N, C, S, TOTAL, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n c = (offs // S) % C\n b = tl.load(bias_ptr + c, mask=mask, other=0.0)\n v = tl.load(x_ptr + offs, mask=mask, other=0.0)\n tl.store(x_ptr + offs, v + b, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, num_classes=1000):\n super(ModelNew, self).__init__()\n self.conv1 = nn.Conv2d(in_channels=3, out_channels=96, kernel_size=11, stride=4, padding=2)\n\n def forward(self, x):\n out = F.conv2d(x, self.conv1.weight, None, stride=4, padding=2)\n out = out.contiguous()\n N, C, H, W = out.shape\n S = H * W\n TOTAL = N * C * S\n BLOCK = 1024\n grid = (triton.cdiv(TOTAL, BLOCK),)\n bias_kernel[grid](out, self.conv1.bias.contiguous(), N, C, S, TOTAL, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L1_083 conv_depthwise_2D_square_input_asymmetric_kernel, 2.43x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef dwconv_kernel(x_ptr, w_ptr, b_ptr, out_ptr,\n N, C, H, W, OH, OW,\n stride, padding, dilation,\n K: tl.constexpr, HAS_BIAS: tl.constexpr, BLOCK: tl.constexpr):\n pid_row = tl.program_id(0)\n pid_col = tl.program_id(1)\n\n oh = pid_row % OH\n tmp = pid_row // OH\n c = tmp % C\n n = tmp // C\n\n ow = pid_col * BLOCK + tl.arange(0, BLOCK)\n mask = ow < OW\n\n iw = ow * stride - padding\n ih0 = oh * stride - padding\n wvalid = mask & (iw >= 0) & (iw < W)\n\n acc = tl.zeros((BLOCK,), tl.float32)\n base = (n.to(tl.int64) * C + c) * H * W\n wbase = c * K\n\n for k in tl.static_range(K):\n ih = ih0 + k * dilation\n if (ih >= 0) & (ih < H):\n idx = base + ih.to(tl.int64) * W + iw\n v = tl.load(x_ptr + idx, mask=wvalid, other=0.0)\n wv = tl.load(w_ptr + wbase + k)\n acc += v * wv\n\n if HAS_BIAS:\n bv = tl.load(b_ptr + c)\n acc += bv\n\n obase = ((n.to(tl.int64) * C + c) * OH + oh) * OW\n tl.store(out_ptr + obase + ow, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, dilation: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv2d = nn.Conv2d(in_channels, in_channels, kernel_size=(kernel_size, 1),\n stride=stride, padding=padding, dilation=dilation,\n groups=in_channels, bias=bias)\n self.in_channels = in_channels\n self.kernel_size = kernel_size\n self.stride = stride\n self.padding = padding\n self.dilation = dilation\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n x = x.contiguous()\n N, C, H, W = x.shape\n K = self.kernel_size\n stride = self.stride\n padding = self.padding\n dilation = self.dilation\n OH = (H + 2 * padding - dilation * (K - 1) - 1) // stride + 1\n OW = (W + 2 * padding - 1) // stride + 1\n out = torch.empty((N, C, OH, OW), device=x.device, dtype=x.dtype)\n w = self.conv2d.weight.contiguous().view(-1)\n if self.has_bias:\n b = self.conv2d.bias.contiguous()\n else:\n b = torch.empty(1, device=x.device, dtype=x.dtype)\n BLOCK = 256\n grid = (N * C * OH, triton.cdiv(OW, BLOCK))\n dwconv_kernel[grid](x, w, b, out,\n N, C, H, W, OH, OW,\n stride, padding, dilation,\n K=K, HAS_BIAS=self.has_bias, BLOCK=BLOCK,\n num_warps=4)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 10864, "ctx_sha": "0b6222244e19e377", "names_self": false, "family": "conv", "level": 1, "name": "conv_standard_3D__square_input__square_kernel", "instruction": "KernelBench level 1 problem L1_054 (conv_standard_3D__square_input__square_kernel), op family: conv.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Performs a standard 3D convolution operation with square input and square kernel.\n\n Args:\n in_channels (int): Number of channels in the input tensor.\n out_channels (int): Number of channels produced by the convolution.\n kernel_size (int): Size of the square convolution kernel.\n stride (int, optional): Stride of the convolution. Defaults to 1.\n padding (int, optional): Padding applied to the input. Defaults to 0.\n dilation (int, optional): Spacing between kernel elements. Defaults to 1.\n groups (int, optional): Number of blocked connections from input channels to output channels. Defaults to 1.\n bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.\n \"\"\"\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, dilation: int = 1, groups: int = 1, bias: bool = False):\n super(Model, self).__init__()\n self.conv3d = nn.Conv3d(in_channels, out_channels, (kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias)\n \n def forward(self, x: torch.Tensor) -> torch.Tensor:\n \"\"\"\n Performs the 3D convolution.\n\n Args:\n x (torch.Tensor): Input tensor of shape (batch_size, in_channels, depth, width, height).\n\n Returns:\n torch.Tensor: Output tensor of shape (batch_size, out_channels, depth_out, width_out, height_out).\n \"\"\"\n return self.conv3d(x)\n\n# Test code\nbatch_size = 16\nin_channels = 3\nout_channels = 64\nkernel_size = 3\ndepth = 64\nwidth = 64\nheight = 64\n\ndef get_inputs():\n x = torch.rand(batch_size, in_channels, depth, width, height)\n return [x]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size] # Provide in_channels, out_channels, kernel_size for initialization```\n"}, "L1_060": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L1_050 conv_standard_2D__square_input__square_kernel, 1.00x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef bias_kernel(x_ptr, bias_ptr, N, C, S, TOTAL, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n c = (offs // S) % C\n b = tl.load(bias_ptr + c, mask=mask, other=0.0)\n v = tl.load(x_ptr + offs, mask=mask, other=0.0)\n tl.store(x_ptr + offs, v + b, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, num_classes=1000):\n super(ModelNew, self).__init__()\n self.conv1 = nn.Conv2d(in_channels=3, out_channels=96, kernel_size=11, stride=4, padding=2)\n\n def forward(self, x):\n out = F.conv2d(x, self.conv1.weight, None, stride=4, padding=2)\n out = out.contiguous()\n N, C, H, W = out.shape\n S = H * W\n TOTAL = N * C * S\n BLOCK = 1024\n grid = (triton.cdiv(TOTAL, BLOCK),)\n bias_kernel[grid](out, self.conv1.bias.contiguous(), N, C, S, TOTAL, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L1_083 conv_depthwise_2D_square_input_asymmetric_kernel, 2.43x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef dwconv_kernel(x_ptr, w_ptr, b_ptr, out_ptr,\n N, C, H, W, OH, OW,\n stride, padding, dilation,\n K: tl.constexpr, HAS_BIAS: tl.constexpr, BLOCK: tl.constexpr):\n pid_row = tl.program_id(0)\n pid_col = tl.program_id(1)\n\n oh = pid_row % OH\n tmp = pid_row // OH\n c = tmp % C\n n = tmp // C\n\n ow = pid_col * BLOCK + tl.arange(0, BLOCK)\n mask = ow < OW\n\n iw = ow * stride - padding\n ih0 = oh * stride - padding\n wvalid = mask & (iw >= 0) & (iw < W)\n\n acc = tl.zeros((BLOCK,), tl.float32)\n base = (n.to(tl.int64) * C + c) * H * W\n wbase = c * K\n\n for k in tl.static_range(K):\n ih = ih0 + k * dilation\n if (ih >= 0) & (ih < H):\n idx = base + ih.to(tl.int64) * W + iw\n v = tl.load(x_ptr + idx, mask=wvalid, other=0.0)\n wv = tl.load(w_ptr + wbase + k)\n acc += v * wv\n\n if HAS_BIAS:\n bv = tl.load(b_ptr + c)\n acc += bv\n\n obase = ((n.to(tl.int64) * C + c) * OH + oh) * OW\n tl.store(out_ptr + obase + ow, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, dilation: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv2d = nn.Conv2d(in_channels, in_channels, kernel_size=(kernel_size, 1),\n stride=stride, padding=padding, dilation=dilation,\n groups=in_channels, bias=bias)\n self.in_channels = in_channels\n self.kernel_size = kernel_size\n self.stride = stride\n self.padding = padding\n self.dilation = dilation\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n x = x.contiguous()\n N, C, H, W = x.shape\n K = self.kernel_size\n stride = self.stride\n padding = self.padding\n dilation = self.dilation\n OH = (H + 2 * padding - dilation * (K - 1) - 1) // stride + 1\n OW = (W + 2 * padding - 1) // stride + 1\n out = torch.empty((N, C, OH, OW), device=x.device, dtype=x.dtype)\n w = self.conv2d.weight.contiguous().view(-1)\n if self.has_bias:\n b = self.conv2d.bias.contiguous()\n else:\n b = torch.empty(1, device=x.device, dtype=x.dtype)\n BLOCK = 256\n grid = (N * C * OH, triton.cdiv(OW, BLOCK))\n dwconv_kernel[grid](x, w, b, out,\n N, C, H, W, OH, OW,\n stride, padding, dilation,\n K=K, HAS_BIAS=self.has_bias, BLOCK=BLOCK,\n num_warps=4)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L1_050 conv_standard_2D__square_input__square_kernel, 1.00x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef bias_kernel(x_ptr, bias_ptr, N, C, S, TOTAL, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n c = (offs // S) % C\n b = tl.load(bias_ptr + c, mask=mask, other=0.0)\n v = tl.load(x_ptr + offs, mask=mask, other=0.0)\n tl.store(x_ptr + offs, v + b, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, num_classes=1000):\n super(ModelNew, self).__init__()\n self.conv1 = nn.Conv2d(in_channels=3, out_channels=96, kernel_size=11, stride=4, padding=2)\n\n def forward(self, x):\n out = F.conv2d(x, self.conv1.weight, None, stride=4, padding=2)\n out = out.contiguous()\n N, C, H, W = out.shape\n S = H * W\n TOTAL = N * C * S\n BLOCK = 1024\n grid = (triton.cdiv(TOTAL, BLOCK),)\n bias_kernel[grid](out, self.conv1.bias.contiguous(), N, C, S, TOTAL, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L1_083 conv_depthwise_2D_square_input_asymmetric_kernel, 2.43x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef dwconv_kernel(x_ptr, w_ptr, b_ptr, out_ptr,\n N, C, H, W, OH, OW,\n stride, padding, dilation,\n K: tl.constexpr, HAS_BIAS: tl.constexpr, BLOCK: tl.constexpr):\n pid_row = tl.program_id(0)\n pid_col = tl.program_id(1)\n\n oh = pid_row % OH\n tmp = pid_row // OH\n c = tmp % C\n n = tmp // C\n\n ow = pid_col * BLOCK + tl.arange(0, BLOCK)\n mask = ow < OW\n\n iw = ow * stride - padding\n ih0 = oh * stride - padding\n wvalid = mask & (iw >= 0) & (iw < W)\n\n acc = tl.zeros((BLOCK,), tl.float32)\n base = (n.to(tl.int64) * C + c) * H * W\n wbase = c * K\n\n for k in tl.static_range(K):\n ih = ih0 + k * dilation\n if (ih >= 0) & (ih < H):\n idx = base + ih.to(tl.int64) * W + iw\n v = tl.load(x_ptr + idx, mask=wvalid, other=0.0)\n wv = tl.load(w_ptr + wbase + k)\n acc += v * wv\n\n if HAS_BIAS:\n bv = tl.load(b_ptr + c)\n acc += bv\n\n obase = ((n.to(tl.int64) * C + c) * OH + oh) * OW\n tl.store(out_ptr + obase + ow, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, dilation: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv2d = nn.Conv2d(in_channels, in_channels, kernel_size=(kernel_size, 1),\n stride=stride, padding=padding, dilation=dilation,\n groups=in_channels, bias=bias)\n self.in_channels = in_channels\n self.kernel_size = kernel_size\n self.stride = stride\n self.padding = padding\n self.dilation = dilation\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n x = x.contiguous()\n N, C, H, W = x.shape\n K = self.kernel_size\n stride = self.stride\n padding = self.padding\n dilation = self.dilation\n OH = (H + 2 * padding - dilation * (K - 1) - 1) // stride + 1\n OW = (W + 2 * padding - 1) // stride + 1\n out = torch.empty((N, C, OH, OW), device=x.device, dtype=x.dtype)\n w = self.conv2d.weight.contiguous().view(-1)\n if self.has_bias:\n b = self.conv2d.bias.contiguous()\n else:\n b = torch.empty(1, device=x.device, dtype=x.dtype)\n BLOCK = 256\n grid = (N * C * OH, triton.cdiv(OW, BLOCK))\n dwconv_kernel[grid](x, w, b, out,\n N, C, H, W, OH, OW,\n stride, padding, dilation,\n K=K, HAS_BIAS=self.has_bias, BLOCK=BLOCK,\n num_warps=4)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 10864, "ctx_sha": "0b6222244e19e377", "names_self": false, "family": "conv", "level": 1, "name": "conv_standard_3D__square_input__asymmetric_kernel", "instruction": "KernelBench level 1 problem L1_060 (conv_standard_3D__square_input__asymmetric_kernel), op family: conv.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Performs a standard 3D convolution operation with a square input and an asymmetric kernel.\n\n Args:\n in_channels (int): Number of channels in the input tensor.\n out_channels (int): Number of channels produced by the convolution.\n kernel_size (tuple): Size of the convolution kernel (kernel_width, kernel_height, kernel_depth).\n stride (int, optional): Stride of the convolution. Defaults to 1.\n padding (int or tuple, optional): Padding applied to the input. Defaults to 0.\n dilation (int or tuple, optional): Spacing between kernel elements. Defaults to 1.\n groups (int, optional): Number of blocked connections from input channels to output channels. Defaults to 1.\n bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.\n \"\"\"\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple, stride: int = 1, padding: int = 0, dilation: int = 1, groups: int = 1, bias: bool = False):\n super(Model, self).__init__()\n self.conv3d = nn.Conv3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias)\n \n def forward(self, x: torch.Tensor) -> torch.Tensor:\n \"\"\"\n Performs the 3D convolution.\n\n Args:\n x (torch.Tensor): Input tensor of shape (batch_size, in_channels, width, height, depth).\n\n Returns:\n torch.Tensor: Output tensor of shape (batch_size, out_channels, width_out, height_out, depth_out).\n \"\"\"\n return self.conv3d(x)\n\n# Test code\nbatch_size = 16\nin_channels = 3\nout_channels = 64\nkernel_size = (3, 5, 7) # Asymmetric kernel\nwidth = 64\nheight = 64\ndepth = 64\n\ndef get_inputs():\n x = torch.rand(batch_size, in_channels, width, height, depth)\n return [x]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size] # Provide in_channels, out_channels, kernel_size for initialization```\n"}, "L1_070": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```"}, "same_for_readers": true, "ctx_chars": 11175, "ctx_sha": "5e031feda794c122", "names_self": false, "family": "conv_transpose", "level": 1, "name": "conv_transposed_3D__asymmetric_input__square_kernel", "instruction": "KernelBench level 1 problem L1_070 (conv_transposed_3D__asymmetric_input__square_kernel), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Performs a transposed 3D convolution operation with asymmetric input and a square kernel.\n\n Args:\n in_channels (int): Number of channels in the input tensor.\n out_channels (int): Number of channels produced by the convolution.\n kernel_size (int): Size of the square convolution kernel.\n stride (int or tuple, optional): Stride of the convolution. Defaults to 1.\n padding (int or tuple, optional): Padding applied to the input. Defaults to 0.\n output_padding (int or tuple, optional): Additional size added to one side of each dimension in the output shape. \n Defaults to 0.\n dilation (int or tuple, optional): Spacing between kernel elements. Defaults to 1.\n groups (int, optional): Number of blocked connections from input channels to output channels. Defaults to 1.\n bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.\n \"\"\"\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, \n dilation: int = 1, groups: int = 1, bias: bool = False):\n super(Model, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, (kernel_size, kernel_size, kernel_size), \n stride=stride, padding=padding, output_padding=output_padding, \n dilation=dilation, groups=groups, bias=bias)\n \n def forward(self, x: torch.Tensor) -> torch.Tensor:\n \"\"\"\n Performs the transposed 3D convolution.\n\n Args:\n x (torch.Tensor): Input tensor of shape (batch_size, in_channels, depth, height, width).\n\n Returns:\n torch.Tensor: Output tensor of shape (batch_size, out_channels, depth_out, height_out, width_out).\n \"\"\"\n return self.conv_transpose3d(x)\n\n# Test code\nbatch_size = 8\nin_channels = 48\nout_channels = 24\nkernel_size = 3\ndepth = 96\nheight = 96\nwidth = 96\n\ndef get_inputs():\n x = torch.rand(batch_size, in_channels, depth, height, width)\n return [x]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size] # Provide in_channels, out_channels, kernel_size for initialization```\n"}, "L1_073": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```"}, "same_for_readers": true, "ctx_chars": 11175, "ctx_sha": "5e031feda794c122", "names_self": false, "family": "conv_transpose", "level": 1, "name": "conv_transposed_3D_asymmetric_input_square_kernel__strided_padded__grouped", "instruction": "KernelBench level 1 problem L1_073 (conv_transposed_3D_asymmetric_input_square_kernel__strided_padded__grouped), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Performs a 3D transposed convolution operation with asymmetric input and square kernel.\n The input is padded before the convolution.\n\n Args:\n in_channels (int): Number of channels in the input tensor.\n out_channels (int): Number of channels produced by the convolution.\n kernel_size (int): Size of the square convolution kernel.\n stride (int, optional): Stride of the convolution. Defaults to 1.\n padding (int, optional): Padding applied to the input. Defaults to 0.\n groups (int, optional): Number of blocked connections from input channels to output channels. Defaults to 1.\n bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.\n \"\"\"\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(Model, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, groups=groups, bias=bias)\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n \"\"\"\n Performs the 3D transposed convolution.\n\n Args:\n x (torch.Tensor): Input tensor of shape (batch_size, in_channels, depth, height, width).\n\n Returns:\n torch.Tensor: Output tensor of shape (batch_size, out_channels, depth_out, height_out, width_out).\n \"\"\"\n return self.conv_transpose3d(x)\n\n# Test code\nbatch_size = 4\nin_channels = 32\nout_channels = 32\nkernel_size = 3\ndepth = 32\nheight = 64\nwidth = 128\nstride = 2\npadding = 1\ngroups = 4\n\ndef get_inputs():\n x = torch.rand(batch_size, in_channels, depth, height, width)\n return [x]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, stride, padding, groups]```\n"}, "L1_075": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```"}, "same_for_readers": true, "ctx_chars": 11175, "ctx_sha": "91e4a03c424736b2", "names_self": false, "family": "conv_transpose", "level": 1, "name": "conv_transposed_2D_asymmetric_input_asymmetric_kernel_strided__grouped____padded____dilated__", "instruction": "KernelBench level 1 problem L1_075 (conv_transposed_2D_asymmetric_input_asymmetric_kernel_strided__grouped____padded____dilated__), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Performs a 2D transposed convolution operation with asymmetric input, asymmetric kernel, \n grouped, padded, and dilated.\n\n Args:\n in_channels (int): Number of channels in the input tensor.\n out_channels (int): Number of channels produced by the convolution.\n kernel_size (tuple): Size of the convolution kernel (height, width).\n stride (tuple, optional): Stride of the convolution (height, width). Defaults to (1, 1).\n padding (tuple, optional): Padding applied to the input (height, width). Defaults to (0, 0).\n dilation (tuple, optional): Spacing between kernel elements (height, width). Defaults to (1, 1).\n groups (int, optional): Number of blocked connections from input channels to output channels. Defaults to 1.\n bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.\n \"\"\"\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple, stride: tuple = (1, 1), padding: tuple = (0, 0), dilation: tuple = (1, 1), groups: int = 1, bias: bool = False):\n super(Model, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias)\n \n def forward(self, x: torch.Tensor) -> torch.Tensor:\n \"\"\"\n Performs the 2D transposed convolution.\n\n Args:\n x (torch.Tensor): Input tensor of shape (batch_size, in_channels, height, width).\n\n Returns:\n torch.Tensor: Output tensor of shape (batch_size, out_channels, height_out, width_out).\n \"\"\"\n return self.conv_transpose2d(x)\n\n# Test code\nbatch_size = 16\nin_channels = 32\nout_channels = 64\nkernel_size = (3, 5)\nheight = 128\nwidth = 256\nstride = (2, 3)\npadding = (1, 2)\ndilation = (2, 1)\ngroups = 4\n\ndef get_inputs():\n x = torch.rand(batch_size, in_channels, height, width)\n return [x]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, stride, padding, dilation, groups]```\n"}, "L1_079": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```"}, "same_for_readers": true, "ctx_chars": 11175, "ctx_sha": "91e4a03c424736b2", "names_self": false, "family": "conv_transpose", "level": 1, "name": "conv_transposed_1D_asymmetric_input_square_kernel___padded____strided____dilated__", "instruction": "KernelBench level 1 problem L1_079 (conv_transposed_1D_asymmetric_input_square_kernel___padded____strided____dilated__), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Performs a transposed 1D convolution operation with asymmetric input and square kernel.\n Supports padding, striding, and dilation.\n\n Args:\n in_channels (int): Number of channels in the input tensor.\n out_channels (int): Number of channels produced by the convolution.\n kernel_size (int): Size of the square convolution kernel.\n stride (int, optional): Stride of the convolution. Defaults to 1.\n padding (int, optional): Padding applied to the input. Defaults to 0.\n dilation (int, optional): Spacing between kernel elements. Defaults to 1.\n bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.\n \"\"\"\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, dilation: int = 1, bias: bool = False):\n super(Model, self).__init__()\n self.conv1d_transpose = nn.ConvTranspose1d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, bias=bias)\n \n def forward(self, x: torch.Tensor) -> torch.Tensor:\n \"\"\"\n Performs the transposed 1D convolution.\n\n Args:\n x (torch.Tensor): Input tensor of shape (batch_size, in_channels, length).\n\n Returns:\n torch.Tensor: Output tensor of shape (batch_size, out_channels, length_out).\n \"\"\"\n return self.conv1d_transpose(x)\n\n# Test code\nbatch_size = 16\nin_channels = 32\nout_channels = 64\nkernel_size = 3\n# long sequence\nlength = 131072\nstride = 2\npadding = 1\ndilation = 2\n\ndef get_inputs():\n x = torch.rand(batch_size, in_channels, length)\n return [x]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, stride, padding, dilation]```\n"}, "L1_081": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L1_078 conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__, 2.29x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n oc = t % OC\n ic = t // OC\n src = ((ic * OC + oc) * KH + kh) * KW + kw\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((oc * IC + ic) * KH + fkh) * KW + fkw\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,\n stride: tuple = (1, 1), padding: tuple = (0, 0), bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,\n stride=stride, padding=padding, bias=bias)\n self.stride = stride\n self.padding = padding\n self.kernel_size = kernel_size\n self.in_channels = in_channels\n self.out_channels = out_channels\n self.has_bias = bias\n\n def forward(self, x):\n stride_ok = (self.stride == (1, 1) or self.stride == 1)\n if stride_ok and x.is_cuda:\n w = self.conv_transpose2d.weight # (IC, OC, KH, KW)\n IC, OC, KH, KW = w.shape\n wf = torch.empty((OC, IC, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KH, KW, BLOCK=BLOCK)\n pad_h = KH - 1 - self.padding[0]\n pad_w = KW - 1 - self.padding[1]\n b = self.conv_transpose2d.bias if self.has_bias else None\n return torch.nn.functional.conv2d(x, wf, bias=b, stride=1,\n padding=(pad_h, pad_w))\n return self.conv_transpose2d(x)\n```\n\n### A verified kernel for a related conv_transpose problem (L1_061 conv_transposed_3D__square_input__square_kernel, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef flip_kernel(w_ptr, o_ptr, IC, OC, KD, KH, KW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = IC * OC * KD * KH * KW\n mask = offs < total\n o = offs\n kw = o % KW\n t = o // KW\n kh = t % KH\n t = t // KH\n kd = t % KD\n t = t // KD\n oc = t % OC\n ic = t // OC\n src = ((((ic * OC + oc) * KD + kd) * KH + kh) * KW + kw)\n fkd = KD - 1 - kd\n fkh = KH - 1 - kh\n fkw = KW - 1 - kw\n dst = ((((oc * IC + ic) * KD + fkd) * KH + fkh) * KW + fkw)\n v = tl.load(w_ptr + src, mask=mask, other=0.0)\n tl.store(o_ptr + dst, v, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.conv_transpose3d = nn.ConvTranspose3d(in_channels, out_channels, kernel_size=(kernel_size, kernel_size, kernel_size), stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)\n self.stride = stride\n self.padding = padding\n self.output_padding = output_padding\n self.groups = groups\n self.has_bias = bias\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n simple = (self.stride == 1 and self.output_padding == 0 and self.groups == 1 and x.is_cuda)\n if simple:\n w = self.conv_transpose3d.weight # (IC, OC, KD, KH, KW)\n IC, OC, KD, KH, KW = w.shape\n wf = torch.empty((OC, IC, KD, KH, KW), device=w.device, dtype=w.dtype)\n total = IC * OC * KD * KH * KW\n BLOCK = 256\n flip_kernel[(triton.cdiv(total, BLOCK),)](\n w.contiguous(), wf, IC, OC, KD, KH, KW, BLOCK=BLOCK)\n p = KD - 1 - self.padding\n b = self.conv_transpose3d.bias if self.has_bias else None\n return F.conv3d(x, wf, bias=b, stride=1, padding=(p, p, p))\n return self.conv_transpose3d(x)\n```"}, "same_for_readers": true, "ctx_chars": 11175, "ctx_sha": "91e4a03c424736b2", "names_self": false, "family": "conv_transpose", "level": 1, "name": "conv_transposed_2D_asymmetric_input_square_kernel___dilated____padded____strided__", "instruction": "KernelBench level 1 problem L1_081 (conv_transposed_2D_asymmetric_input_square_kernel___dilated____padded____strided__), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Performs a 2D transposed convolution operation with asymmetric input and square kernel, supporting dilation, padding, and stride.\n\n Args:\n in_channels (int): Number of channels in the input tensor.\n out_channels (int): Number of channels produced by the convolution.\n kernel_size (int): Size of the convolution kernel (square, e.g., 3 for a 3x3 kernel).\n stride (int, optional): Stride of the convolution. Defaults to 1.\n padding (int, optional): Padding applied to the input. Defaults to 0.\n dilation (int, optional): Spacing between kernel elements. Defaults to 1.\n bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.\n \"\"\"\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, dilation: int = 1, bias: bool = False):\n super(Model, self).__init__()\n self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, bias=bias)\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n \"\"\"\n Performs the 2D transposed convolution.\n\n Args:\n x (torch.Tensor): Input tensor of shape (batch_size, in_channels, height_in, width_in). \n\n Returns:\n torch.Tensor: Output tensor of shape (batch_size, out_channels, height_out, width_out).\n \"\"\"\n return self.conv_transpose2d(x)\n\n\n# Test code\nbatch_size = 16\nin_channels = 32\nout_channels = 64\nkernel_size = 3\nheight_in = 64\nwidth_in = 128\nstride = 5\npadding = 1\ndilation = 2\n\ndef get_inputs():\n x = torch.rand(batch_size, in_channels, height_in, width_in)\n return [x]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, stride, padding, dilation]```\n"}, "L1_098": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel."}, "same_for_readers": true, "ctx_chars": 1982, "ctx_sha": "54e16caf9bef9eec", "names_self": false, "family": "loss", "level": 1, "name": "KLDivLoss", "instruction": "KernelBench level 1 problem L1_098 (KLDivLoss), op family: loss.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n A model that computes Kullback-Leibler Divergence for comparing two distributions.\n\n Parameters:\n None\n \"\"\"\n def __init__(self):\n super(Model, self).__init__()\n\n def forward(self, predictions, targets):\n return torch.nn.functional.kl_div(torch.log(predictions), targets, reduction='batchmean')\n\nbatch_size = 8192 * 2\ninput_shape = (8192 * 2,)\ndim = 1\n\ndef get_inputs():\n scale = torch.rand(())\n return [(torch.rand(batch_size, *input_shape)*scale).softmax(dim=-1), torch.rand(batch_size, *input_shape).softmax(dim=-1)]\n\ndef get_init_inputs():\n return []\n```\n"}, "L2_001": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel."}, "same_for_readers": true, "ctx_chars": 1982, "ctx_sha": "54e16caf9bef9eec", "names_self": false, "family": "activation", "level": 2, "name": "Conv2D_ReLU_BiasAdd", "instruction": "KernelBench level 2 problem L2_001 (Conv2D_ReLU_BiasAdd), op family: activation.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Simple model that performs a convolution, applies ReLU, and adds a bias term.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, bias_shape):\n super(Model, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.bias = nn.Parameter(torch.randn(bias_shape)) \n\n def forward(self, x):\n x = self.conv(x)\n x = torch.relu(x)\n x = x + self.bias\n return x\n\nbatch_size = 128\nin_channels = 64 \nout_channels = 128 \nheight = width = 128\nkernel_size = 3\nbias_shape = (out_channels, 1, 1)\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, height, width)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, bias_shape]```\n"}, "L2_007": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L2_043 Conv3d_Max_LogSumExp_ReLU, 1.02x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, out_ptr, N, C, D, H, W, Dp, Hp, Wp,\n NOUT, BLOCK: tl.constexpr, C_CONST: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < NOUT\n npw = Hp * Wp\n nplane = Dp * npw\n n = offs // nplane\n rem = offs % nplane\n dp = rem // npw\n rem2 = rem % npw\n hp = rem2 // Wp\n wp = rem2 % Wp\n d0 = dp * 2\n h0 = hp * 2\n w0 = wp * 2\n HW = H * W\n S = D * HW\n nbase = n.to(tl.int64) * C * S\n\n run_max = tl.full((BLOCK,), -1e30, tl.float32)\n run_sum = tl.zeros((BLOCK,), tl.float32)\n for c in range(C_CONST):\n cbase = nbase + c * S\n m = tl.full((BLOCK,), -1e30, tl.float32)\n for kd in range(2):\n for kh in range(2):\n for kw in range(2):\n off = cbase + (d0 + kd).to(tl.int64) * HW + (h0 + kh) * W + (w0 + kw)\n v = tl.load(x_ptr + off, mask=mask, other=-1e30)\n m = tl.maximum(m, v)\n new_max = tl.maximum(run_max, m)\n run_sum = run_sum * tl.exp(run_max - new_max) + tl.exp(m - new_max)\n run_max = new_max\n lse = run_max + tl.log(run_sum)\n lse = tl.maximum(lse, 0.0)\n tl.store(out_ptr + offs, lse, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.out_channels = out_channels\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, D, H, W = x.shape\n Dp, Hp, Wp = D // 2, H // 2, W // 2\n out = torch.empty((N, 1, Dp, Hp, Wp), device=x.device, dtype=x.dtype)\n NOUT = N * Dp * Hp * Wp\n BLOCK = 256\n grid = (triton.cdiv(NOUT, BLOCK),)\n fused_kernel[grid](x, out, N, C, D, H, W, Dp, Hp, Wp,\n NOUT, BLOCK=BLOCK, C_CONST=C)\n return out\n```\n\n### A verified kernel for a related conv problem (L2_048 Conv3d_Scaling_Tanh_Multiply_Sigmoid, 1.33x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, scale_ptr, bias_ptr, out_ptr,\n TOTAL, C, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n c = (offs // S) % C\n s = tl.load(scale_ptr + c, mask=mask, other=0.0)\n b = tl.load(bias_ptr + c, mask=mask, other=0.0)\n x = tl.load(x_ptr + offs, mask=mask, other=0.0)\n t = tl.extra.cuda.libdevice.tanh(x * s)\n t = t * b\n out = 1.0 / (1.0 + tl.exp(-t))\n tl.store(out_ptr + offs, out, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, scaling_factor, bias_shape):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv3d(in_channels, out_channels, kernel_size)\n self.scaling_factor = nn.Parameter(torch.randn(bias_shape))\n self.bias = nn.Parameter(torch.randn(bias_shape))\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, D, H, W = x.shape\n S = D * H * W\n TOTAL = x.numel()\n out = torch.empty_like(x)\n BLOCK = 1024\n grid = (triton.cdiv(TOTAL, BLOCK),)\n fused_kernel[grid](x, self.scaling_factor.contiguous().view(-1),\n self.bias.contiguous().view(-1), out,\n TOTAL, C, S, BLOCK=BLOCK)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L2_043 Conv3d_Max_LogSumExp_ReLU, 1.02x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, out_ptr, N, C, D, H, W, Dp, Hp, Wp,\n NOUT, BLOCK: tl.constexpr, C_CONST: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < NOUT\n npw = Hp * Wp\n nplane = Dp * npw\n n = offs // nplane\n rem = offs % nplane\n dp = rem // npw\n rem2 = rem % npw\n hp = rem2 // Wp\n wp = rem2 % Wp\n d0 = dp * 2\n h0 = hp * 2\n w0 = wp * 2\n HW = H * W\n S = D * HW\n nbase = n.to(tl.int64) * C * S\n\n run_max = tl.full((BLOCK,), -1e30, tl.float32)\n run_sum = tl.zeros((BLOCK,), tl.float32)\n for c in range(C_CONST):\n cbase = nbase + c * S\n m = tl.full((BLOCK,), -1e30, tl.float32)\n for kd in range(2):\n for kh in range(2):\n for kw in range(2):\n off = cbase + (d0 + kd).to(tl.int64) * HW + (h0 + kh) * W + (w0 + kw)\n v = tl.load(x_ptr + off, mask=mask, other=-1e30)\n m = tl.maximum(m, v)\n new_max = tl.maximum(run_max, m)\n run_sum = run_sum * tl.exp(run_max - new_max) + tl.exp(m - new_max)\n run_max = new_max\n lse = run_max + tl.log(run_sum)\n lse = tl.maximum(lse, 0.0)\n tl.store(out_ptr + offs, lse, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.out_channels = out_channels\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, D, H, W = x.shape\n Dp, Hp, Wp = D // 2, H // 2, W // 2\n out = torch.empty((N, 1, Dp, Hp, Wp), device=x.device, dtype=x.dtype)\n NOUT = N * Dp * Hp * Wp\n BLOCK = 256\n grid = (triton.cdiv(NOUT, BLOCK),)\n fused_kernel[grid](x, out, N, C, D, H, W, Dp, Hp, Wp,\n NOUT, BLOCK=BLOCK, C_CONST=C)\n return out\n```\n\n### A verified kernel for a related conv problem (L2_048 Conv3d_Scaling_Tanh_Multiply_Sigmoid, 1.33x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, scale_ptr, bias_ptr, out_ptr,\n TOTAL, C, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n c = (offs // S) % C\n s = tl.load(scale_ptr + c, mask=mask, other=0.0)\n b = tl.load(bias_ptr + c, mask=mask, other=0.0)\n x = tl.load(x_ptr + offs, mask=mask, other=0.0)\n t = tl.extra.cuda.libdevice.tanh(x * s)\n t = t * b\n out = 1.0 / (1.0 + tl.exp(-t))\n tl.store(out_ptr + offs, out, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, scaling_factor, bias_shape):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv3d(in_channels, out_channels, kernel_size)\n self.scaling_factor = nn.Parameter(torch.randn(bias_shape))\n self.bias = nn.Parameter(torch.randn(bias_shape))\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, D, H, W = x.shape\n S = D * H * W\n TOTAL = x.numel()\n out = torch.empty_like(x)\n BLOCK = 1024\n grid = (triton.cdiv(TOTAL, BLOCK),)\n fused_kernel[grid](x, self.scaling_factor.contiguous().view(-1),\n self.bias.contiguous().view(-1), out,\n TOTAL, C, S, BLOCK=BLOCK)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 10508, "ctx_sha": "4fa7857ea4c0dcf4", "names_self": false, "family": "conv", "level": 2, "name": "Conv3d_ReLU_LeakyReLU_GELU_Sigmoid_BiasAdd", "instruction": "KernelBench level 2 problem L2_007 (Conv3d_ReLU_LeakyReLU_GELU_Sigmoid_BiasAdd), op family: conv.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Model that performs a 3D convolution, applies ReLU, LeakyReLU, GELU, Sigmoid activations, and bias in sequence.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, bias_shape):\n super(Model, self).__init__()\n self.conv = nn.Conv3d(in_channels, out_channels, kernel_size)\n self.bias = nn.Parameter(torch.randn(bias_shape)) \n\n def forward(self, x):\n x = self.conv(x)\n x = torch.relu(x)\n x = torch.nn.functional.leaky_relu(x, negative_slope=0.01)\n x = torch.nn.functional.gelu(x)\n x = torch.sigmoid(x)\n x = x + self.bias\n return x\n\nbatch_size = 64\nin_channels = 8\nout_channels = 32\ndepth, height, width = 32, 64, 64\nkernel_size = 3\nbias_shape = (out_channels, 1, 1, 1)\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, depth, height, width)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, bias_shape]```\n"}, "L2_010": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_011 ConvTranspose2d_BatchNorm_Tanh_MaxPool_GroupNorm, 1.05x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef reduce_nc(x_ptr, sum_ptr, sq_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = tl.arange(0, BLOCK)\n base = pid * S\n acc = tl.zeros((), dtype=tl.float32)\n accsq = tl.zeros((), dtype=tl.float32)\n for i in range(0, S, BLOCK):\n idx = i + offs\n m = idx < S\n v = tl.load(x_ptr + base + idx, mask=m, other=0.0)\n acc += tl.sum(v)\n accsq += tl.sum(v * v)\n tl.store(sum_ptr + pid, acc)\n tl.store(sq_ptr + pid, accsq)\n\n\n@triton.jit\ndef bn_tanh_pool(x_ptr, out_ptr, scale_ptr, shift_ptr,\n N, C, H, W, Ho, Wo, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * Ho * Wo\n m = offs < total\n wo = offs % Wo\n t = offs // Wo\n ho = t % Ho\n t = t // Ho\n c = t % C\n n = t // C\n\n sc = tl.load(scale_ptr + c, mask=m, other=0.0)\n sh = tl.load(shift_ptr + c, mask=m, other=0.0)\n\n hbase = ho * 2\n wbase = wo * 2\n inbase = ((n * C + c) * H + hbase) * W + wbase\n\n v00 = tl.load(x_ptr + inbase, mask=m, other=-1e30)\n v01 = tl.load(x_ptr + inbase + 1, mask=m, other=-1e30)\n v10 = tl.load(x_ptr + inbase + W, mask=m, other=-1e30)\n v11 = tl.load(x_ptr + inbase + W + 1, mask=m, other=-1e30)\n\n t00 = tl.extra.cuda.libdevice.tanh(sc * v00 + sh)\n t01 = tl.extra.cuda.libdevice.tanh(sc * v01 + sh)\n t10 = tl.extra.cuda.libdevice.tanh(sc * v10 + sh)\n t11 = tl.extra.cuda.libdevice.tanh(sc * v11 + sh)\n\n mx = tl.maximum(tl.maximum(t00, t01), tl.maximum(t10, t11))\n tl.store(out_ptr + offs, mx, mask=m)\n\n\n@triton.jit\ndef gn_apply(y_ptr, out_ptr, mean_ptr, inv_ptr, w_ptr, b_ptr,\n N, C, So, cpg, GPC, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * So\n m = offs < total\n t = offs // So\n c = t % C\n n = t // C\n g = c // cpg\n ng = n * GPC + g\n\n mean = tl.load(mean_ptr + ng, mask=m, other=0.0)\n inv = tl.load(inv_ptr + ng, mask=m, other=0.0)\n w = tl.load(w_ptr + c, mask=m, other=0.0)\n b = tl.load(b_ptr + c, mask=m, other=0.0)\n v = tl.load(y_ptr + offs, mask=m, other=0.0)\n r = (v - mean) * inv * w + b\n tl.store(out_ptr + offs, r, mask=m)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, groups, num_groups):\n super(ModelNew, self).__init__()\n self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.batch_norm = nn.BatchNorm2d(out_channels)\n self.max_pool = nn.MaxPool2d(kernel_size=2, stride=2)\n self.group_norm = nn.GroupNorm(num_groups=num_groups, num_channels=out_channels)\n self.num_groups = num_groups\n\n def forward(self, x):\n c = self.conv_transpose(x)\n N, C, H, W = c.shape\n c = c.contiguous()\n S = H * W\n c2 = c.view(N * C, S)\n\n ssum = torch.empty(N * C, device=c.device, dtype=torch.float32)\n ssq = torch.empty(N * C, device=c.device, dtype=torch.float32)\n reduce_nc[(N * C,)](c2, ssum, ssq, S, BLOCK=1024)\n\n ssum = ssum.view(N, C)\n ssq = ssq.view(N, C)\n M = N * S\n mean_c = ssum.sum(0) / M\n var_c = ssq.sum(0) / M - mean_c * mean_c\n scale_c = (self.batch_norm.weight / torch.sqrt(var_c + self.batch_norm.eps)).contiguous()\n shift_c = (self.batch_norm.bias - mean_c * scale_c).contiguous()\n\n Ho = H // 2\n Wo = W // 2\n y = torch.empty(N, C, Ho, Wo, device=c.device, dtype=torch.float32)\n total = N * C * Ho * Wo\n grid = ((total + 255) // 256,)\n bn_tanh_pool[grid](c, y, scale_c, shift_c, N, C, H, W, Ho, Wo, BLOCK=256)\n\n # group norm\n G = self.num_groups\n cpg = C // G\n So = Ho * Wo\n seg = cpg * So\n yv = y.view(N * G, seg)\n gsum = torch.empty(N * G, device=c.device, dtype=torch.float32)\n gsq = torch.empty(N * G, device=c.device, dtype=torch.float32)\n reduce_nc[(N * G,)](yv, gsum, gsq, seg, BLOCK=1024)\n gmean = gsum / seg\n gvar = gsq / seg - gmean * gmean\n ginv = 1.0 / torch.sqrt(gvar + self.group_norm.eps)\n\n out = torch.empty_like(y)\n totalg = N * C * So\n gridg = ((totalg + 255) // 256,)\n gn_apply[gridg](y, out, gmean.contiguous(), ginv.contiguous(),\n self.group_norm.weight.contiguous(), self.group_norm.bias.contiguous(),\n N, C, So, cpg, G, BLOCK=256)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_089 ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max, 1.06x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, sub_ptr, out_ptr, N, C, S, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n mask = idx < total\n\n # idx indexes (n, s) flat where s in [0,S)\n n = idx // S\n s = idx % S\n base = n * C * S + s\n\n # pass 1: max over channels\n mx = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=-1e30)\n mx = tl.maximum(mx, v)\n\n # pass 2: sum of exp\n sm = tl.zeros((BLOCK,), tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sm += tl.exp(v - mx)\n\n # pass 3: softmax, subtract, swish, max over channels\n res = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sub = tl.load(sub_ptr + c)\n sm_val = tl.exp(v - mx) / sm\n y = sm_val - sub\n swish = (tl.sigmoid(y) * y)\n res = tl.maximum(res, swish)\n\n tl.store(out_ptr + idx, res, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, pool_kernel_size, pool_stride, pool_padding):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.max_pool = nn.MaxPool3d(kernel_size=pool_kernel_size, stride=pool_stride, padding=pool_padding)\n self.subtract = nn.Parameter(torch.randn(out_channels))\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = self.max_pool(x).contiguous()\n N, C, D, H, W = x.shape\n S = D * H * W\n total = N * S\n\n out = torch.empty((N, D, H, W), device=x.device, dtype=x.dtype)\n sub = self.subtract.contiguous()\n\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n fused_kernel[grid](x, sub, out, N, C, S, total, BLOCK=BLOCK)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_011 ConvTranspose2d_BatchNorm_Tanh_MaxPool_GroupNorm, 1.05x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef reduce_nc(x_ptr, sum_ptr, sq_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = tl.arange(0, BLOCK)\n base = pid * S\n acc = tl.zeros((), dtype=tl.float32)\n accsq = tl.zeros((), dtype=tl.float32)\n for i in range(0, S, BLOCK):\n idx = i + offs\n m = idx < S\n v = tl.load(x_ptr + base + idx, mask=m, other=0.0)\n acc += tl.sum(v)\n accsq += tl.sum(v * v)\n tl.store(sum_ptr + pid, acc)\n tl.store(sq_ptr + pid, accsq)\n\n\n@triton.jit\ndef bn_tanh_pool(x_ptr, out_ptr, scale_ptr, shift_ptr,\n N, C, H, W, Ho, Wo, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * Ho * Wo\n m = offs < total\n wo = offs % Wo\n t = offs // Wo\n ho = t % Ho\n t = t // Ho\n c = t % C\n n = t // C\n\n sc = tl.load(scale_ptr + c, mask=m, other=0.0)\n sh = tl.load(shift_ptr + c, mask=m, other=0.0)\n\n hbase = ho * 2\n wbase = wo * 2\n inbase = ((n * C + c) * H + hbase) * W + wbase\n\n v00 = tl.load(x_ptr + inbase, mask=m, other=-1e30)\n v01 = tl.load(x_ptr + inbase + 1, mask=m, other=-1e30)\n v10 = tl.load(x_ptr + inbase + W, mask=m, other=-1e30)\n v11 = tl.load(x_ptr + inbase + W + 1, mask=m, other=-1e30)\n\n t00 = tl.extra.cuda.libdevice.tanh(sc * v00 + sh)\n t01 = tl.extra.cuda.libdevice.tanh(sc * v01 + sh)\n t10 = tl.extra.cuda.libdevice.tanh(sc * v10 + sh)\n t11 = tl.extra.cuda.libdevice.tanh(sc * v11 + sh)\n\n mx = tl.maximum(tl.maximum(t00, t01), tl.maximum(t10, t11))\n tl.store(out_ptr + offs, mx, mask=m)\n\n\n@triton.jit\ndef gn_apply(y_ptr, out_ptr, mean_ptr, inv_ptr, w_ptr, b_ptr,\n N, C, So, cpg, GPC, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * So\n m = offs < total\n t = offs // So\n c = t % C\n n = t // C\n g = c // cpg\n ng = n * GPC + g\n\n mean = tl.load(mean_ptr + ng, mask=m, other=0.0)\n inv = tl.load(inv_ptr + ng, mask=m, other=0.0)\n w = tl.load(w_ptr + c, mask=m, other=0.0)\n b = tl.load(b_ptr + c, mask=m, other=0.0)\n v = tl.load(y_ptr + offs, mask=m, other=0.0)\n r = (v - mean) * inv * w + b\n tl.store(out_ptr + offs, r, mask=m)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, groups, num_groups):\n super(ModelNew, self).__init__()\n self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.batch_norm = nn.BatchNorm2d(out_channels)\n self.max_pool = nn.MaxPool2d(kernel_size=2, stride=2)\n self.group_norm = nn.GroupNorm(num_groups=num_groups, num_channels=out_channels)\n self.num_groups = num_groups\n\n def forward(self, x):\n c = self.conv_transpose(x)\n N, C, H, W = c.shape\n c = c.contiguous()\n S = H * W\n c2 = c.view(N * C, S)\n\n ssum = torch.empty(N * C, device=c.device, dtype=torch.float32)\n ssq = torch.empty(N * C, device=c.device, dtype=torch.float32)\n reduce_nc[(N * C,)](c2, ssum, ssq, S, BLOCK=1024)\n\n ssum = ssum.view(N, C)\n ssq = ssq.view(N, C)\n M = N * S\n mean_c = ssum.sum(0) / M\n var_c = ssq.sum(0) / M - mean_c * mean_c\n scale_c = (self.batch_norm.weight / torch.sqrt(var_c + self.batch_norm.eps)).contiguous()\n shift_c = (self.batch_norm.bias - mean_c * scale_c).contiguous()\n\n Ho = H // 2\n Wo = W // 2\n y = torch.empty(N, C, Ho, Wo, device=c.device, dtype=torch.float32)\n total = N * C * Ho * Wo\n grid = ((total + 255) // 256,)\n bn_tanh_pool[grid](c, y, scale_c, shift_c, N, C, H, W, Ho, Wo, BLOCK=256)\n\n # group norm\n G = self.num_groups\n cpg = C // G\n So = Ho * Wo\n seg = cpg * So\n yv = y.view(N * G, seg)\n gsum = torch.empty(N * G, device=c.device, dtype=torch.float32)\n gsq = torch.empty(N * G, device=c.device, dtype=torch.float32)\n reduce_nc[(N * G,)](yv, gsum, gsq, seg, BLOCK=1024)\n gmean = gsum / seg\n gvar = gsq / seg - gmean * gmean\n ginv = 1.0 / torch.sqrt(gvar + self.group_norm.eps)\n\n out = torch.empty_like(y)\n totalg = N * C * So\n gridg = ((totalg + 255) // 256,)\n gn_apply[gridg](y, out, gmean.contiguous(), ginv.contiguous(),\n self.group_norm.weight.contiguous(), self.group_norm.bias.contiguous(),\n N, C, So, cpg, G, BLOCK=256)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_089 ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max, 1.06x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, sub_ptr, out_ptr, N, C, S, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n mask = idx < total\n\n # idx indexes (n, s) flat where s in [0,S)\n n = idx // S\n s = idx % S\n base = n * C * S + s\n\n # pass 1: max over channels\n mx = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=-1e30)\n mx = tl.maximum(mx, v)\n\n # pass 2: sum of exp\n sm = tl.zeros((BLOCK,), tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sm += tl.exp(v - mx)\n\n # pass 3: softmax, subtract, swish, max over channels\n res = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sub = tl.load(sub_ptr + c)\n sm_val = tl.exp(v - mx) / sm\n y = sm_val - sub\n swish = (tl.sigmoid(y) * y)\n res = tl.maximum(res, swish)\n\n tl.store(out_ptr + idx, res, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, pool_kernel_size, pool_stride, pool_padding):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.max_pool = nn.MaxPool3d(kernel_size=pool_kernel_size, stride=pool_stride, padding=pool_padding)\n self.subtract = nn.Parameter(torch.randn(out_channels))\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = self.max_pool(x).contiguous()\n N, C, D, H, W = x.shape\n S = D * H * W\n total = N * S\n\n out = torch.empty((N, D, H, W), device=x.device, dtype=x.dtype)\n sub = self.subtract.contiguous()\n\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n fused_kernel[grid](x, sub, out, N, C, S, total, BLOCK=BLOCK)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 13707, "ctx_sha": "c2fd2e75f0a9c4ac", "names_self": false, "family": "conv_transpose", "level": 2, "name": "ConvTranspose2d_MaxPool_Hardtanh_Mean_Tanh", "instruction": "KernelBench level 2 problem L2_010 (ConvTranspose2d_MaxPool_Hardtanh_Mean_Tanh), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Model that performs a transposed convolution, followed by max pooling, hardtanh activation, mean operation, and tanh activation.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, maxpool_kernel_size, maxpool_stride, hardtanh_min, hardtanh_max):\n super(Model, self).__init__()\n self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.maxpool = nn.MaxPool2d(kernel_size=maxpool_kernel_size, stride=maxpool_stride)\n self.hardtanh = nn.Hardtanh(min_val=hardtanh_min, max_val=hardtanh_max)\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = self.maxpool(x)\n x = self.hardtanh(x)\n x = torch.mean(x, dim=(2, 3), keepdim=True)\n x = torch.tanh(x)\n return x\n\nbatch_size = 128\nin_channels = 64 \nout_channels = 64 \nheight = width = 256 \nkernel_size = 3\nstride = 1\npadding = 1\nmaxpool_kernel_size = 2\nmaxpool_stride = 2\nhardtanh_min = -1\nhardtanh_max = 1\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, height, width)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, stride, padding, maxpool_kernel_size, maxpool_stride, hardtanh_min, hardtanh_max]```\n"}, "L2_017": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L2_073 Conv2d_BatchNorm_Scaling, 1.68x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef stats_kernel2(x_ptr, sum_ptr, sumsq_ptr, N, C, S, SBLK: tl.constexpr):\n c = tl.program_id(0)\n sblk = tl.program_id(1)\n offs = sblk * SBLK + tl.arange(0, SBLK)\n smask = offs < S\n acc_sum = tl.zeros((SBLK,), tl.float32)\n acc_sq = tl.zeros((SBLK,), tl.float32)\n cS = c.to(tl.int64) * S\n NCS = C * S\n for n in range(N):\n base = n.to(tl.int64) * NCS + cS + offs\n v = tl.load(x_ptr + base, mask=smask, other=0.0)\n acc_sum += v\n acc_sq += v * v\n s = tl.sum(acc_sum, axis=0)\n sq = tl.sum(acc_sq, axis=0)\n tl.atomic_add(sum_ptr + c, s)\n tl.atomic_add(sumsq_ptr + c, sq)\n\n\n@triton.jit\ndef bn_apply_kernel(x_ptr, out_ptr, mean_ptr, invstd_ptr, w_ptr, b_ptr,\n scaling, C, S, TOTAL, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n c = (offs // S) % C\n v = tl.load(x_ptr + offs, mask=mask, other=0.0)\n mean = tl.load(mean_ptr + c, mask=mask, other=0.0)\n invstd = tl.load(invstd_ptr + c, mask=mask, other=0.0)\n w = tl.load(w_ptr + c, mask=mask, other=0.0)\n b = tl.load(b_ptr + c, mask=mask, other=0.0)\n r = ((v - mean) * invstd * w + b) * scaling\n tl.store(out_ptr + offs, r, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, scaling_factor):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.bn = nn.BatchNorm2d(out_channels)\n self.scaling_factor = scaling_factor\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n count = N * S\n device = x.device\n\n sums = torch.zeros(C, device=device, dtype=torch.float32)\n sumsq = torch.zeros(C, device=device, dtype=torch.float32)\n SBLK = 1024\n nsblk = triton.cdiv(S, SBLK)\n stats_kernel2[(C, nsblk)](x, sums, sumsq, N, C, S, SBLK=SBLK)\n\n if self.training:\n mean = sums / count\n var = sumsq / count - mean * mean\n with torch.no_grad():\n self.bn.running_mean.mul_(1 - self.bn.momentum).add_(self.bn.momentum * mean.detach())\n unbiased = var * count / (count - 1)\n self.bn.running_var.mul_(1 - self.bn.momentum).add_(self.bn.momentum * unbiased.detach())\n else:\n mean = self.bn.running_mean\n var = self.bn.running_var\n\n invstd = torch.rsqrt(var + self.bn.eps)\n w = self.bn.weight\n b = self.bn.bias\n\n out = torch.empty_like(x)\n TOTAL = x.numel()\n BLOCK = 1024\n grid = (triton.cdiv(TOTAL, BLOCK),)\n bn_apply_kernel[grid](x, out, mean.contiguous(), invstd.contiguous(),\n w.contiguous(), b.contiguous(),\n float(self.scaling_factor), C, S, TOTAL, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L2_067 Conv2d_GELU_GlobalAvgPool, 1.30x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\nfrom triton.language.extra import libdevice\n\n\n@triton.jit\ndef gelu_avg_kernel(x_ptr, out_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n base = pid.to(tl.int64) * S\n acc = 0.0\n for off in range(0, S, BLOCK):\n offs = off + tl.arange(0, BLOCK)\n mask = offs < S\n v = tl.load(x_ptr + base + offs, mask=mask, other=0.0)\n g = 0.5 * v * (1.0 + libdevice.erf(v * 0.7071067811865476))\n acc += tl.sum(g, axis=0)\n tl.store(out_ptr + pid, acc / S)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n out = torch.empty((N, C), device=x.device, dtype=x.dtype)\n grid = (N * C,)\n gelu_avg_kernel[grid](x, out, S, BLOCK=1024)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L2_073 Conv2d_BatchNorm_Scaling, 1.68x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef stats_kernel2(x_ptr, sum_ptr, sumsq_ptr, N, C, S, SBLK: tl.constexpr):\n c = tl.program_id(0)\n sblk = tl.program_id(1)\n offs = sblk * SBLK + tl.arange(0, SBLK)\n smask = offs < S\n acc_sum = tl.zeros((SBLK,), tl.float32)\n acc_sq = tl.zeros((SBLK,), tl.float32)\n cS = c.to(tl.int64) * S\n NCS = C * S\n for n in range(N):\n base = n.to(tl.int64) * NCS + cS + offs\n v = tl.load(x_ptr + base, mask=smask, other=0.0)\n acc_sum += v\n acc_sq += v * v\n s = tl.sum(acc_sum, axis=0)\n sq = tl.sum(acc_sq, axis=0)\n tl.atomic_add(sum_ptr + c, s)\n tl.atomic_add(sumsq_ptr + c, sq)\n\n\n@triton.jit\ndef bn_apply_kernel(x_ptr, out_ptr, mean_ptr, invstd_ptr, w_ptr, b_ptr,\n scaling, C, S, TOTAL, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n c = (offs // S) % C\n v = tl.load(x_ptr + offs, mask=mask, other=0.0)\n mean = tl.load(mean_ptr + c, mask=mask, other=0.0)\n invstd = tl.load(invstd_ptr + c, mask=mask, other=0.0)\n w = tl.load(w_ptr + c, mask=mask, other=0.0)\n b = tl.load(b_ptr + c, mask=mask, other=0.0)\n r = ((v - mean) * invstd * w + b) * scaling\n tl.store(out_ptr + offs, r, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, scaling_factor):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.bn = nn.BatchNorm2d(out_channels)\n self.scaling_factor = scaling_factor\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n count = N * S\n device = x.device\n\n sums = torch.zeros(C, device=device, dtype=torch.float32)\n sumsq = torch.zeros(C, device=device, dtype=torch.float32)\n SBLK = 1024\n nsblk = triton.cdiv(S, SBLK)\n stats_kernel2[(C, nsblk)](x, sums, sumsq, N, C, S, SBLK=SBLK)\n\n if self.training:\n mean = sums / count\n var = sumsq / count - mean * mean\n with torch.no_grad():\n self.bn.running_mean.mul_(1 - self.bn.momentum).add_(self.bn.momentum * mean.detach())\n unbiased = var * count / (count - 1)\n self.bn.running_var.mul_(1 - self.bn.momentum).add_(self.bn.momentum * unbiased.detach())\n else:\n mean = self.bn.running_mean\n var = self.bn.running_var\n\n invstd = torch.rsqrt(var + self.bn.eps)\n w = self.bn.weight\n b = self.bn.bias\n\n out = torch.empty_like(x)\n TOTAL = x.numel()\n BLOCK = 1024\n grid = (triton.cdiv(TOTAL, BLOCK),)\n bn_apply_kernel[grid](x, out, mean.contiguous(), invstd.contiguous(),\n w.contiguous(), b.contiguous(),\n float(self.scaling_factor), C, S, TOTAL, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L2_067 Conv2d_GELU_GlobalAvgPool, 1.30x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\nfrom triton.language.extra import libdevice\n\n\n@triton.jit\ndef gelu_avg_kernel(x_ptr, out_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n base = pid.to(tl.int64) * S\n acc = 0.0\n for off in range(0, S, BLOCK):\n offs = off + tl.arange(0, BLOCK)\n mask = offs < S\n v = tl.load(x_ptr + base + offs, mask=mask, other=0.0)\n g = 0.5 * v * (1.0 + libdevice.erf(v * 0.7071067811865476))\n acc += tl.sum(g, axis=0)\n tl.store(out_ptr + pid, acc / S)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n out = torch.empty((N, C), device=x.device, dtype=x.dtype)\n grid = (N * C,)\n gelu_avg_kernel[grid](x, out, S, BLOCK=1024)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 11132, "ctx_sha": "4caa9b6e3a0949e1", "names_self": false, "family": "conv", "level": 2, "name": "Conv2d_InstanceNorm_Divide", "instruction": "KernelBench level 2 problem L2_017 (Conv2d_InstanceNorm_Divide), op family: conv.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Simple model that performs a convolution, applies Instance Normalization, and divides by a constant.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, divide_by):\n super(Model, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.instance_norm = nn.InstanceNorm2d(out_channels)\n self.divide_by = divide_by\n\n def forward(self, x):\n x = self.conv(x)\n x = self.instance_norm(x)\n x = x / self.divide_by\n return x\n\nbatch_size = 128\nin_channels = 64 \nout_channels = 128 \nheight = width = 128 \nkernel_size = 3\ndivide_by = 2.0\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, height, width)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, divide_by]```\n"}, "L2_021": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L2_085 Conv2d_GroupNorm_Scale_MaxPool_Clamp, 1.61x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef stats_kernel(x_ptr, mean_ptr, invstd_ptr, N, C, S, G, CPG, eps, BLOCK: tl.constexpr):\n pid = tl.program_id(0) # n*G + g\n n = pid // G\n g = pid % G\n GS = CPG * S\n base = n.to(tl.int64) * C * S + g.to(tl.int64) * CPG * S\n offs = tl.arange(0, BLOCK)\n acc_s = tl.zeros((BLOCK,), tl.float32)\n acc_sq = tl.zeros((BLOCK,), tl.float32)\n for start in range(0, GS, BLOCK):\n idx = start + offs\n mask = idx < GS\n v = tl.load(x_ptr + base + idx, mask=mask, other=0.0)\n acc_s += tl.where(mask, v, 0.0)\n acc_sq += tl.where(mask, v * v, 0.0)\n s = tl.sum(acc_s, axis=0)\n sq = tl.sum(acc_sq, axis=0)\n mean = s / GS\n var = sq / GS - mean * mean\n tl.store(mean_ptr + pid, mean)\n tl.store(invstd_ptr + pid, 1.0 / tl.sqrt(var + eps))\n\n\n@triton.jit\ndef fused_kernel(x_ptr, out_ptr, mean_ptr, invstd_ptr, w_ptr, b_ptr, scale_ptr,\n N, C, H, W, OH, OW, P, G, CPG,\n clamp_min, clamp_max, TOTAL, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n ow = offs % OW\n tmp = offs // OW\n oh = tmp % OH\n tmp = tmp // OH\n c = tmp % C\n n = tmp // C\n g = c // CPG\n stat_idx = n * G + g\n mean = tl.load(mean_ptr + stat_idx, mask=mask, other=0.0)\n invstd = tl.load(invstd_ptr + stat_idx, mask=mask, other=0.0)\n w = tl.load(w_ptr + c, mask=mask, other=0.0)\n b = tl.load(b_ptr + c, mask=mask, other=0.0)\n sc = tl.load(scale_ptr + c, mask=mask, other=0.0)\n\n base = (n.to(tl.int64) * C + c) * H * W\n h0 = oh * P\n w0 = ow * P\n acc = tl.full((BLOCK,), -3.4e38, tl.float32)\n for ph in range(0, P):\n for pw in range(0, P):\n ih = h0 + ph\n iw = w0 + pw\n vmask = mask & (ih < H) & (iw < W)\n v = tl.load(x_ptr + base + ih.to(tl.int64) * W + iw, mask=vmask, other=-3.4e38)\n vn = ((v - mean) * invstd * w + b) * sc\n acc = tl.maximum(acc, vn)\n acc = tl.minimum(tl.maximum(acc, clamp_min), clamp_max)\n tl.store(out_ptr + offs, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, num_groups, scale_shape, maxpool_kernel_size, clamp_min, clamp_max):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.group_norm = nn.GroupNorm(num_groups, out_channels)\n self.scale = nn.Parameter(torch.ones(scale_shape))\n self.maxpool = nn.MaxPool2d(kernel_size=maxpool_kernel_size)\n self.clamp_min = clamp_min\n self.clamp_max = clamp_max\n self.num_groups = num_groups\n self.pool_k = maxpool_kernel_size\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n G = self.num_groups\n CPG = C // G\n\n mean = torch.empty(N * G, device=x.device, dtype=torch.float32)\n invstd = torch.empty(N * G, device=x.device, dtype=torch.float32)\n stats_kernel[(N * G,)](x, mean, invstd, N, C, S, G, CPG,\n float(self.group_norm.eps), BLOCK=1024)\n\n P = self.pool_k\n OH = H // P\n OW = W // P\n out = torch.empty((N, C, OH, OW), device=x.device, dtype=torch.float32)\n TOTAL = out.numel()\n BLOCK = 256\n grid = (triton.cdiv(TOTAL, BLOCK),)\n fused_kernel[grid](x, out, mean, invstd,\n self.group_norm.weight.contiguous(),\n self.group_norm.bias.contiguous(),\n self.scale.contiguous().view(-1),\n N, C, H, W, OH, OW, P, G, CPG,\n float(self.clamp_min), float(self.clamp_max),\n TOTAL, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L2_092 Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp, 2.37x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\nfrom triton.language.extra.cuda import libdevice\n\n\n@triton.jit\ndef gn_stats_kernel(x_ptr, mean_ptr, invstd_ptr, CPG, S, GS, eps, BLOCK: tl.constexpr):\n pid = tl.program_id(0) # over n*groups\n base = pid.to(tl.int64) * GS\n acc = 0.0\n acc2 = 0.0\n for off in range(0, GS, BLOCK):\n offs = off + tl.arange(0, BLOCK)\n mask = offs < GS\n v = tl.load(x_ptr + base + offs, mask=mask, other=0.0)\n acc += tl.sum(v, axis=0)\n acc2 += tl.sum(v * v, axis=0)\n mean = acc / GS\n var = acc2 / GS - mean * mean\n invstd = 1.0 / tl.sqrt(var + eps)\n tl.store(mean_ptr + pid, mean)\n tl.store(invstd_ptr + pid, invstd)\n\n\n@triton.jit\ndef fused_kernel(x_ptr, mean_ptr, invstd_ptr, gamma_ptr, beta_ptr, out_ptr,\n N, C, S, NS, G, CPG, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < NS\n n = offs // S\n s = offs % S\n base = n.to(tl.int64) * C * S + s\n maxv = tl.full((BLOCK,), -3.4e38, tl.float32)\n for c in range(C):\n g = c // CPG\n ng = n * G + g\n xc = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n mean = tl.load(mean_ptr + ng, mask=mask, other=0.0)\n invstd = tl.load(invstd_ptr + ng, mask=mask, other=0.0)\n gamma = tl.load(gamma_ptr + c)\n beta = tl.load(beta_ptr + c)\n norm = (xc - mean) * invstd * gamma + beta\n t = libdevice.tanh(norm)\n hs = t * tl.minimum(tl.maximum(t + 3.0, 0.0), 6.0) / 6.0\n res = xc + hs\n maxv = tl.maximum(maxv, res)\n sumexp = tl.zeros((BLOCK,), tl.float32)\n for c in range(C):\n g = c // CPG\n ng = n * G + g\n xc = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n mean = tl.load(mean_ptr + ng, mask=mask, other=0.0)\n invstd = tl.load(invstd_ptr + ng, mask=mask, other=0.0)\n gamma = tl.load(gamma_ptr + c)\n beta = tl.load(beta_ptr + c)\n norm = (xc - mean) * invstd * gamma + beta\n t = libdevice.tanh(norm)\n hs = t * tl.minimum(tl.maximum(t + 3.0, 0.0), 6.0) / 6.0\n res = xc + hs\n sumexp += tl.exp(res - maxv)\n out = maxv + tl.log(sumexp)\n tl.store(out_ptr + offs, out, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, groups, eps=1e-5):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.group_norm = nn.GroupNorm(groups, out_channels, eps=eps)\n self.tanh = nn.Tanh()\n self.hard_swish = nn.Hardswish()\n self.groups = groups\n self.eps = eps\n\n def forward(self, x):\n x_conv = self.conv(x).contiguous()\n N, C, H, W = x_conv.shape\n S = H * W\n G = self.groups\n CPG = C // G\n GS = CPG * S\n mean = torch.empty((N * G,), device=x_conv.device, dtype=torch.float32)\n invstd = torch.empty((N * G,), device=x_conv.device, dtype=torch.float32)\n gn_stats_kernel[(N * G,)](x_conv, mean, invstd, CPG, S, GS, self.eps, BLOCK=1024)\n out = torch.empty((N, 1, H, W), device=x_conv.device, dtype=x_conv.dtype)\n NS = N * S\n BLOCK = 256\n grid = (triton.cdiv(NS, BLOCK),)\n fused_kernel[grid](x_conv, mean, invstd,\n self.group_norm.weight, self.group_norm.bias,\n out, N, C, S, NS, G, CPG, BLOCK=BLOCK)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L2_085 Conv2d_GroupNorm_Scale_MaxPool_Clamp, 1.61x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef stats_kernel(x_ptr, mean_ptr, invstd_ptr, N, C, S, G, CPG, eps, BLOCK: tl.constexpr):\n pid = tl.program_id(0) # n*G + g\n n = pid // G\n g = pid % G\n GS = CPG * S\n base = n.to(tl.int64) * C * S + g.to(tl.int64) * CPG * S\n offs = tl.arange(0, BLOCK)\n acc_s = tl.zeros((BLOCK,), tl.float32)\n acc_sq = tl.zeros((BLOCK,), tl.float32)\n for start in range(0, GS, BLOCK):\n idx = start + offs\n mask = idx < GS\n v = tl.load(x_ptr + base + idx, mask=mask, other=0.0)\n acc_s += tl.where(mask, v, 0.0)\n acc_sq += tl.where(mask, v * v, 0.0)\n s = tl.sum(acc_s, axis=0)\n sq = tl.sum(acc_sq, axis=0)\n mean = s / GS\n var = sq / GS - mean * mean\n tl.store(mean_ptr + pid, mean)\n tl.store(invstd_ptr + pid, 1.0 / tl.sqrt(var + eps))\n\n\n@triton.jit\ndef fused_kernel(x_ptr, out_ptr, mean_ptr, invstd_ptr, w_ptr, b_ptr, scale_ptr,\n N, C, H, W, OH, OW, P, G, CPG,\n clamp_min, clamp_max, TOTAL, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < TOTAL\n ow = offs % OW\n tmp = offs // OW\n oh = tmp % OH\n tmp = tmp // OH\n c = tmp % C\n n = tmp // C\n g = c // CPG\n stat_idx = n * G + g\n mean = tl.load(mean_ptr + stat_idx, mask=mask, other=0.0)\n invstd = tl.load(invstd_ptr + stat_idx, mask=mask, other=0.0)\n w = tl.load(w_ptr + c, mask=mask, other=0.0)\n b = tl.load(b_ptr + c, mask=mask, other=0.0)\n sc = tl.load(scale_ptr + c, mask=mask, other=0.0)\n\n base = (n.to(tl.int64) * C + c) * H * W\n h0 = oh * P\n w0 = ow * P\n acc = tl.full((BLOCK,), -3.4e38, tl.float32)\n for ph in range(0, P):\n for pw in range(0, P):\n ih = h0 + ph\n iw = w0 + pw\n vmask = mask & (ih < H) & (iw < W)\n v = tl.load(x_ptr + base + ih.to(tl.int64) * W + iw, mask=vmask, other=-3.4e38)\n vn = ((v - mean) * invstd * w + b) * sc\n acc = tl.maximum(acc, vn)\n acc = tl.minimum(tl.maximum(acc, clamp_min), clamp_max)\n tl.store(out_ptr + offs, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, num_groups, scale_shape, maxpool_kernel_size, clamp_min, clamp_max):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.group_norm = nn.GroupNorm(num_groups, out_channels)\n self.scale = nn.Parameter(torch.ones(scale_shape))\n self.maxpool = nn.MaxPool2d(kernel_size=maxpool_kernel_size)\n self.clamp_min = clamp_min\n self.clamp_max = clamp_max\n self.num_groups = num_groups\n self.pool_k = maxpool_kernel_size\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n G = self.num_groups\n CPG = C // G\n\n mean = torch.empty(N * G, device=x.device, dtype=torch.float32)\n invstd = torch.empty(N * G, device=x.device, dtype=torch.float32)\n stats_kernel[(N * G,)](x, mean, invstd, N, C, S, G, CPG,\n float(self.group_norm.eps), BLOCK=1024)\n\n P = self.pool_k\n OH = H // P\n OW = W // P\n out = torch.empty((N, C, OH, OW), device=x.device, dtype=torch.float32)\n TOTAL = out.numel()\n BLOCK = 256\n grid = (triton.cdiv(TOTAL, BLOCK),)\n fused_kernel[grid](x, out, mean, invstd,\n self.group_norm.weight.contiguous(),\n self.group_norm.bias.contiguous(),\n self.scale.contiguous().view(-1),\n N, C, H, W, OH, OW, P, G, CPG,\n float(self.clamp_min), float(self.clamp_max),\n TOTAL, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L2_092 Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp, 2.37x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\nfrom triton.language.extra.cuda import libdevice\n\n\n@triton.jit\ndef gn_stats_kernel(x_ptr, mean_ptr, invstd_ptr, CPG, S, GS, eps, BLOCK: tl.constexpr):\n pid = tl.program_id(0) # over n*groups\n base = pid.to(tl.int64) * GS\n acc = 0.0\n acc2 = 0.0\n for off in range(0, GS, BLOCK):\n offs = off + tl.arange(0, BLOCK)\n mask = offs < GS\n v = tl.load(x_ptr + base + offs, mask=mask, other=0.0)\n acc += tl.sum(v, axis=0)\n acc2 += tl.sum(v * v, axis=0)\n mean = acc / GS\n var = acc2 / GS - mean * mean\n invstd = 1.0 / tl.sqrt(var + eps)\n tl.store(mean_ptr + pid, mean)\n tl.store(invstd_ptr + pid, invstd)\n\n\n@triton.jit\ndef fused_kernel(x_ptr, mean_ptr, invstd_ptr, gamma_ptr, beta_ptr, out_ptr,\n N, C, S, NS, G, CPG, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < NS\n n = offs // S\n s = offs % S\n base = n.to(tl.int64) * C * S + s\n maxv = tl.full((BLOCK,), -3.4e38, tl.float32)\n for c in range(C):\n g = c // CPG\n ng = n * G + g\n xc = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n mean = tl.load(mean_ptr + ng, mask=mask, other=0.0)\n invstd = tl.load(invstd_ptr + ng, mask=mask, other=0.0)\n gamma = tl.load(gamma_ptr + c)\n beta = tl.load(beta_ptr + c)\n norm = (xc - mean) * invstd * gamma + beta\n t = libdevice.tanh(norm)\n hs = t * tl.minimum(tl.maximum(t + 3.0, 0.0), 6.0) / 6.0\n res = xc + hs\n maxv = tl.maximum(maxv, res)\n sumexp = tl.zeros((BLOCK,), tl.float32)\n for c in range(C):\n g = c // CPG\n ng = n * G + g\n xc = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n mean = tl.load(mean_ptr + ng, mask=mask, other=0.0)\n invstd = tl.load(invstd_ptr + ng, mask=mask, other=0.0)\n gamma = tl.load(gamma_ptr + c)\n beta = tl.load(beta_ptr + c)\n norm = (xc - mean) * invstd * gamma + beta\n t = libdevice.tanh(norm)\n hs = t * tl.minimum(tl.maximum(t + 3.0, 0.0), 6.0) / 6.0\n res = xc + hs\n sumexp += tl.exp(res - maxv)\n out = maxv + tl.log(sumexp)\n tl.store(out_ptr + offs, out, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, groups, eps=1e-5):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.group_norm = nn.GroupNorm(groups, out_channels, eps=eps)\n self.tanh = nn.Tanh()\n self.hard_swish = nn.Hardswish()\n self.groups = groups\n self.eps = eps\n\n def forward(self, x):\n x_conv = self.conv(x).contiguous()\n N, C, H, W = x_conv.shape\n S = H * W\n G = self.groups\n CPG = C // G\n GS = CPG * S\n mean = torch.empty((N * G,), device=x_conv.device, dtype=torch.float32)\n invstd = torch.empty((N * G,), device=x_conv.device, dtype=torch.float32)\n gn_stats_kernel[(N * G,)](x_conv, mean, invstd, CPG, S, GS, self.eps, BLOCK=1024)\n out = torch.empty((N, 1, H, W), device=x_conv.device, dtype=x_conv.dtype)\n NS = N * S\n BLOCK = 256\n grid = (triton.cdiv(NS, BLOCK),)\n fused_kernel[grid](x_conv, mean, invstd,\n self.group_norm.weight, self.group_norm.bias,\n out, N, C, S, NS, G, CPG, BLOCK=BLOCK)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 14530, "ctx_sha": "531c6735226f817a", "names_self": false, "family": "conv", "level": 2, "name": "Conv2d_Add_Scale_Sigmoid_GroupNorm", "instruction": "KernelBench level 2 problem L2_021 (Conv2d_Add_Scale_Sigmoid_GroupNorm), op family: conv.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Model that performs a convolution, adds a bias term, scales, applies sigmoid, and performs group normalization.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, num_groups, bias_shape, scale_shape):\n super(Model, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.bias = nn.Parameter(torch.randn(bias_shape)) \n self.scale = nn.Parameter(torch.randn(scale_shape))\n self.group_norm = nn.GroupNorm(num_groups, out_channels)\n\n def forward(self, x):\n x = self.conv(x)\n x = x + self.bias\n x = x * self.scale\n x = torch.sigmoid(x)\n x = self.group_norm(x)\n return x\n\nbatch_size = 128\nin_channels = 8\nout_channels = 32\nheight = width = 256\nkernel_size = 3\nnum_groups = 8\nbias_shape = (out_channels, 1, 1)\nscale_shape = (out_channels, 1, 1)\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, height, width)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, num_groups, bias_shape, scale_shape]```\n"}, "L2_031": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L2_032 Conv2d_Scaling_Min, 1.10x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef scale_min_kernel(x_ptr, out_ptr, scale, C, S, NS, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < NS\n n = offs // S\n s = offs % S\n base = n.to(tl.int64) * C * S + s\n acc = tl.full((BLOCK,), 1e30, tl.float32)\n for c in range(C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=1e30)\n acc = tl.minimum(acc, v)\n acc = acc * scale\n tl.store(out_ptr + offs, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, scale_factor):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.scale_factor = scale_factor\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n out = torch.empty((N, 1, H, W), device=x.device, dtype=x.dtype)\n NS = N * S\n BLOCK = 1024\n grid = (triton.cdiv(NS, BLOCK),)\n scale_min_kernel[grid](x, out, float(self.scale_factor), C, S, NS, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L2_025 Conv2d_Min_Tanh_Tanh, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef min_tanh_kernel(x_ptr, out_ptr, C, S, NS, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < NS\n n = offs // S\n s = offs % S\n base = n.to(tl.int64) * C * S + s\n acc = tl.full((BLOCK,), 1e30, tl.float32)\n for c in range(C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=1e30)\n acc = tl.minimum(acc, v)\n acc = tl.minimum(tl.maximum(acc, -1e30), 1e30)\n t = tl.extra.cuda.libdevice.tanh(acc)\n t = tl.extra.cuda.libdevice.tanh(t)\n tl.store(out_ptr + offs, t, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n out = torch.empty((N, 1, H, W), device=x.device, dtype=x.dtype)\n NS = N * S\n BLOCK = 1024\n grid = (triton.cdiv(NS, BLOCK),)\n min_tanh_kernel[grid](x, out, C, S, NS, BLOCK=BLOCK)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv problems (wrong results or slower than eager)\n- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.\n- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.\n- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.\n- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels \u00d7 contiguous spatial block] so loads coalesce along the innermost dimension.\n- Pitfall: Don't wrap the cuDNN/PyTorch op and then add a no-op copy kernel. The extra full-tensor read/write plus launch only adds time. Write a real fused kernel that replaces or eliminates work.\n\n### Verified recipes for conv problems (speedups measured by the protected evaluator)\n- [2.43x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv with a direct Triton kernel, since cuDNN's depthwise path is slow. Keep nn.Conv2d only as the parameter holder. Use a 2D grid: program 0 covers one (n, c, oh) output row, decoded with div/mod; program 1 covers a BLOCK=256 tile of contiguous ow, using num_warps=4. Unroll the kernel taps with tl.static_range. Load the scalar weight per tap and coalesced input rows with masks for padding bounds. Accumulate in fp32, fuse the optional bias via a constexpr flag, and use int64 base offsets.\n- [2.37x on Conv2d_GroupNorm_Tanh_HardSwish_ResidualAdd_LogSumExp] Keep the conv in cuDNN via torch. Replace the GroupNorm+pointwise+channel-reduction tail with two Triton kernels. (1) A stats kernel with one program per (n, group): the group is a contiguous CPG*S slice, so loop BLOCK=1024 accumulating sum and sum-of-squares in fp32, then emit mean and invstd. (2) A fused kernel with one thread per (n, spatial) position and BLOCK=256 coalesced along spatial. Loop over channels with stride S, normalize, apply the activations, add the residual, and compute a two-pass max/sum-exp logsumexp. Recompute instead of storing intermediates. Use int64 base offsets.\n- [2.25x on conv_depthwise_2D_square_input_asymmetric_kernel] Replace cuDNN depthwise/grouped conv (slow in fp32) with a Triton direct-convolution kernel. Use one flattened 1D grid over NCHW outputs with BLOCK\u2248256. Decode n, c, oh, ow by div/mod so adjacent lanes read adjacent ow for coalesced loads. Loop over the small kernel taps, masking out-of-range input coordinates (handles padding/stride/dilation). Load the per-channel weight scalar and add bias under a constexpr flag. Accumulate in fp32 and compute base offsets in int64. Keep the nn.Conv2d module only for parameter storage.\n- [1.94x on Conv2d_Tanh_Scaling_BiasAdd_Max] Keep the convolution in cuDNN via torch (nn.Conv2d / F.conv2d, contiguous NCHW output). Fuse every following elementwise op (activation, scale, per-channel bias) with the pooling into one Triton kernel. Launch one thread per pooled output element, decoding n,c,oh,ow from a flat index. Loop over the PxP window, load, apply libdevice tanh, scale, add bias, keep a running max, then store once. Use int64 base offsets for large tensors, BLOCK=256 on a 1D grid, and keep all math in fp32.\n- [1.68x on Conv2d_BatchNorm_Scaling] Leave the conv itself to cuDNN via torch. Replace training-mode BatchNorm plus any elementwise tail with two Triton passes. Pass 1 computes per-channel sum and sum-of-squares on a 2D grid (channel, spatial block). Loop over the batch with contiguous, coalesced spatial loads, accumulate in fp32 registers, reduce, then atomic_add per channel. Do mean, var and rsqrt on tiny C-sized tensors in torch, and update running stats with unbiased var. Pass 2 is a flat 1D elementwise kernel with c=(offs//S)%C that fuses normalize, affine and scale. Use int64 offsets.\n- [1.61x on Conv2d_GroupNorm_Scale_MaxPool_Clamp] Keep the conv in cuDNN via torch (F.conv2d / nn.Conv2d). Replace GroupNorm plus the epilogue with two Triton kernels. Kernel 1: one program per (n, group) streams the group's contiguous CPG*H*W slab with BLOCK=1024 vector loads, accumulates sum and sum-of-squares in fp32, and writes mean and invstd. Kernel 2: one thread per pooled output element. Load per-channel affine and scale, normalize each window value, then max-reduce and clamp in registers before a single store. Use int64 base offsets and initialize the max with -3.4e38.\n\n### A verified kernel for a related conv problem (L2_032 Conv2d_Scaling_Min, 1.10x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef scale_min_kernel(x_ptr, out_ptr, scale, C, S, NS, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < NS\n n = offs // S\n s = offs % S\n base = n.to(tl.int64) * C * S + s\n acc = tl.full((BLOCK,), 1e30, tl.float32)\n for c in range(C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=1e30)\n acc = tl.minimum(acc, v)\n acc = acc * scale\n tl.store(out_ptr + offs, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, scale_factor):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.scale_factor = scale_factor\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n out = torch.empty((N, 1, H, W), device=x.device, dtype=x.dtype)\n NS = N * S\n BLOCK = 1024\n grid = (triton.cdiv(NS, BLOCK),)\n scale_min_kernel[grid](x, out, float(self.scale_factor), C, S, NS, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv problem (L2_025 Conv2d_Min_Tanh_Tanh, 1.01x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef min_tanh_kernel(x_ptr, out_ptr, C, S, NS, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < NS\n n = offs // S\n s = offs % S\n base = n.to(tl.int64) * C * S + s\n acc = tl.full((BLOCK,), 1e30, tl.float32)\n for c in range(C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=1e30)\n acc = tl.minimum(acc, v)\n acc = tl.minimum(tl.maximum(acc, -1e30), 1e30)\n t = tl.extra.cuda.libdevice.tanh(acc)\n t = tl.extra.cuda.libdevice.tanh(t)\n tl.store(out_ptr + offs, t, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size):\n super(ModelNew, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n\n def forward(self, x):\n x = self.conv(x).contiguous()\n N, C, H, W = x.shape\n S = H * W\n out = torch.empty((N, 1, H, W), device=x.device, dtype=x.dtype)\n NS = N * S\n BLOCK = 1024\n grid = (triton.cdiv(NS, BLOCK),)\n min_tanh_kernel[grid](x, out, C, S, NS, BLOCK=BLOCK)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 9444, "ctx_sha": "a1ff20f70ebfdfbd", "names_self": false, "family": "conv", "level": 2, "name": "Conv2d_Min_Add_Multiply", "instruction": "KernelBench level 2 problem L2_031 (Conv2d_Min_Add_Multiply), op family: conv.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Simple model that performs a convolution, takes the minimum with a constant, adds a bias term, and multiplies by a scaling factor.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, constant_value, bias_shape, scaling_factor):\n super(Model, self).__init__()\n self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)\n self.constant_value = constant_value\n self.bias = nn.Parameter(torch.randn(bias_shape))\n self.scaling_factor = scaling_factor\n\n def forward(self, x):\n x = self.conv(x)\n x = torch.min(x, torch.tensor(self.constant_value))\n x = x + self.bias\n x = x * self.scaling_factor\n return x\n\nbatch_size = 128\nin_channels = 64\nout_channels = 128\nheight = width = 128\nkernel_size = 3\nconstant_value = 0.5\nbias_shape = (out_channels, 1, 1)\nscaling_factor = 2.0\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, height, width)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, constant_value, bias_shape, scaling_factor]```\n"}, "L2_034": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_003 ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU, 1.26x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef ln_kernel(x_ptr, out_ptr, w_ptr, b_ptr, sw, W, eps, BLOCK: tl.constexpr):\n pid = tl.program_id(0).to(tl.int64)\n offs = tl.arange(0, BLOCK)\n m = offs < W\n base = pid * W\n v = tl.load(x_ptr + base + offs, mask=m, other=0.0) + sw\n mean = tl.sum(v, axis=0) / W\n d = tl.where(m, v - mean, 0.0)\n var = tl.sum(d * d, axis=0) / W\n rstd = 1.0 / tl.sqrt(var + eps)\n w = tl.load(w_ptr + offs, mask=m, other=0.0)\n b = tl.load(b_ptr + offs, mask=m, other=0.0)\n r = d * rstd * w + b\n tl.store(out_ptr + base + offs, r, mask=m)\n\n\n@triton.jit\ndef pool_gelu_kernel(x_ptr, out_ptr, D, H, W, OD, OH, OW, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n idx64 = idx.to(tl.int64)\n mask = idx < total\n ow = idx64 % OW\n t = idx64 // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n nc = t // OD\n\n acc = tl.zeros((BLOCK,), tl.float32)\n for dz in tl.static_range(2):\n for dy in tl.static_range(2):\n for dx in tl.static_range(2):\n iz = od * 2 + dz\n iy = oh * 2 + dy\n ix = ow * 2 + dx\n in_off = ((nc * D + iz) * H + iy) * W + ix\n v = tl.load(x_ptr + in_off, mask=mask, other=0.0)\n acc += v\n acc = acc * 0.125\n gelu = acc * 0.5 * (1.0 + tl.erf(acc * 0.70710678118654752440))\n tl.store(out_ptr + idx64, gelu, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, sum_weight, norm_shape, pool_kernel_size):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.sum_weight = nn.Parameter(torch.tensor(sum_weight))\n self.norm = nn.LayerNorm(norm_shape)\n self.avg_pool = nn.AvgPool3d(kernel_size=pool_kernel_size)\n self.gelu = nn.GELU()\n\n def forward(self, x):\n c = self.conv_transpose(x).contiguous()\n N, C, D, H, W = c.shape\n rows = N * C * D * H\n c2 = c.view(rows, W)\n normed = torch.empty_like(c2)\n BLOCKW = triton.next_power_of_2(W)\n w = self.norm.weight.contiguous()\n b = self.norm.bias.contiguous()\n ln_kernel[(rows,)](c2, normed, w, b, float(self.sum_weight.item()), W, self.norm.eps, BLOCK=BLOCKW)\n normed = normed.view(N, C, D, H, W)\n\n OD, OH, OW = D // 2, H // 2, W // 2\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=c.dtype)\n total = N * C * OD * OH * OW\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n pool_gelu_kernel[grid](normed, out, D, H, W, OD, OH, OW, total, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_072 ConvTranspose3d_BatchNorm_AvgPool_AvgPool, 1.68x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef reduce_kernel(x_ptr, sum_ptr, sqsum_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = tl.arange(0, BLOCK)\n base = pid * S\n acc = tl.zeros((), dtype=tl.float32)\n accsq = tl.zeros((), dtype=tl.float32)\n for i in range(0, S, BLOCK):\n idx = i + offs\n m = idx < S\n v = tl.load(x_ptr + base + idx, mask=m, other=0.0)\n acc += tl.sum(v)\n accsq += tl.sum(v * v)\n tl.store(sum_ptr + pid, acc)\n tl.store(sqsum_ptr + pid, accsq)\n\n\n@triton.jit\ndef pool_kernel(x_ptr, out_ptr, scale_ptr, shift_ptr,\n N, C, D, H, W, OD, OH, OW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * OD * OH * OW\n mask = offs < total\n o = offs.to(tl.int64)\n ow = o % OW\n t = o // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n t = t // OD\n c = t % C\n n = t // C\n\n sc = tl.load(scale_ptr + c, mask=mask, other=0.0)\n sh = tl.load(shift_ptr + c, mask=mask, other=0.0)\n\n HW = H * W\n DHW = D * HW\n base = (n * C + c) * DHW\n\n acc = tl.zeros((BLOCK,), dtype=tl.float32)\n for dd in tl.static_range(4):\n for hh in tl.static_range(4):\n for ww in tl.static_range(4):\n id_ = od * 4 + dd\n ih = oh * 4 + hh\n iw = ow * 4 + ww\n addr = base + id_ * HW + ih * W + iw\n v = tl.load(x_ptr + addr, mask=mask, other=0.0)\n acc += v\n acc = acc * (1.0 / 64.0)\n r = sc * acc + sh\n tl.store(out_ptr + offs, r, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, bias_shape):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.batch_norm = nn.BatchNorm3d(out_channels)\n\n def forward(self, x):\n c = self.conv_transpose(x)\n N, C, D, H, W = c.shape\n S = D * H * W\n c2 = c.contiguous().view(N * C, S)\n\n ssum = torch.empty(N * C, device=c.device, dtype=torch.float32)\n ssq = torch.empty(N * C, device=c.device, dtype=torch.float32)\n reduce_kernel[(N * C,)](c2, ssum, ssq, S, BLOCK=1024)\n\n ssum_nc = ssum.view(N, C)\n ssq_nc = ssq.view(N, C)\n M = N * S\n mean_c = ssum_nc.sum(0) / M\n var_c = ssq_nc.sum(0) / M - mean_c * mean_c\n scale_c = self.batch_norm.weight / torch.sqrt(var_c + self.batch_norm.eps)\n shift_c = self.batch_norm.bias - scale_c * mean_c\n\n OD = D // 4\n OH = H // 4\n OW = W // 4\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=torch.float32)\n total = N * C * OD * OH * OW\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n cc = c.contiguous()\n pool_kernel[grid](cc, out, scale_c.contiguous(), shift_c.contiguous(),\n N, C, D, H, W, OD, OH, OW, BLOCK=BLOCK)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_003 ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU, 1.26x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef ln_kernel(x_ptr, out_ptr, w_ptr, b_ptr, sw, W, eps, BLOCK: tl.constexpr):\n pid = tl.program_id(0).to(tl.int64)\n offs = tl.arange(0, BLOCK)\n m = offs < W\n base = pid * W\n v = tl.load(x_ptr + base + offs, mask=m, other=0.0) + sw\n mean = tl.sum(v, axis=0) / W\n d = tl.where(m, v - mean, 0.0)\n var = tl.sum(d * d, axis=0) / W\n rstd = 1.0 / tl.sqrt(var + eps)\n w = tl.load(w_ptr + offs, mask=m, other=0.0)\n b = tl.load(b_ptr + offs, mask=m, other=0.0)\n r = d * rstd * w + b\n tl.store(out_ptr + base + offs, r, mask=m)\n\n\n@triton.jit\ndef pool_gelu_kernel(x_ptr, out_ptr, D, H, W, OD, OH, OW, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n idx64 = idx.to(tl.int64)\n mask = idx < total\n ow = idx64 % OW\n t = idx64 // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n nc = t // OD\n\n acc = tl.zeros((BLOCK,), tl.float32)\n for dz in tl.static_range(2):\n for dy in tl.static_range(2):\n for dx in tl.static_range(2):\n iz = od * 2 + dz\n iy = oh * 2 + dy\n ix = ow * 2 + dx\n in_off = ((nc * D + iz) * H + iy) * W + ix\n v = tl.load(x_ptr + in_off, mask=mask, other=0.0)\n acc += v\n acc = acc * 0.125\n gelu = acc * 0.5 * (1.0 + tl.erf(acc * 0.70710678118654752440))\n tl.store(out_ptr + idx64, gelu, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, sum_weight, norm_shape, pool_kernel_size):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.sum_weight = nn.Parameter(torch.tensor(sum_weight))\n self.norm = nn.LayerNorm(norm_shape)\n self.avg_pool = nn.AvgPool3d(kernel_size=pool_kernel_size)\n self.gelu = nn.GELU()\n\n def forward(self, x):\n c = self.conv_transpose(x).contiguous()\n N, C, D, H, W = c.shape\n rows = N * C * D * H\n c2 = c.view(rows, W)\n normed = torch.empty_like(c2)\n BLOCKW = triton.next_power_of_2(W)\n w = self.norm.weight.contiguous()\n b = self.norm.bias.contiguous()\n ln_kernel[(rows,)](c2, normed, w, b, float(self.sum_weight.item()), W, self.norm.eps, BLOCK=BLOCKW)\n normed = normed.view(N, C, D, H, W)\n\n OD, OH, OW = D // 2, H // 2, W // 2\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=c.dtype)\n total = N * C * OD * OH * OW\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n pool_gelu_kernel[grid](normed, out, D, H, W, OD, OH, OW, total, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_072 ConvTranspose3d_BatchNorm_AvgPool_AvgPool, 1.68x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef reduce_kernel(x_ptr, sum_ptr, sqsum_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = tl.arange(0, BLOCK)\n base = pid * S\n acc = tl.zeros((), dtype=tl.float32)\n accsq = tl.zeros((), dtype=tl.float32)\n for i in range(0, S, BLOCK):\n idx = i + offs\n m = idx < S\n v = tl.load(x_ptr + base + idx, mask=m, other=0.0)\n acc += tl.sum(v)\n accsq += tl.sum(v * v)\n tl.store(sum_ptr + pid, acc)\n tl.store(sqsum_ptr + pid, accsq)\n\n\n@triton.jit\ndef pool_kernel(x_ptr, out_ptr, scale_ptr, shift_ptr,\n N, C, D, H, W, OD, OH, OW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * OD * OH * OW\n mask = offs < total\n o = offs.to(tl.int64)\n ow = o % OW\n t = o // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n t = t // OD\n c = t % C\n n = t // C\n\n sc = tl.load(scale_ptr + c, mask=mask, other=0.0)\n sh = tl.load(shift_ptr + c, mask=mask, other=0.0)\n\n HW = H * W\n DHW = D * HW\n base = (n * C + c) * DHW\n\n acc = tl.zeros((BLOCK,), dtype=tl.float32)\n for dd in tl.static_range(4):\n for hh in tl.static_range(4):\n for ww in tl.static_range(4):\n id_ = od * 4 + dd\n ih = oh * 4 + hh\n iw = ow * 4 + ww\n addr = base + id_ * HW + ih * W + iw\n v = tl.load(x_ptr + addr, mask=mask, other=0.0)\n acc += v\n acc = acc * (1.0 / 64.0)\n r = sc * acc + sh\n tl.store(out_ptr + offs, r, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, bias_shape):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.batch_norm = nn.BatchNorm3d(out_channels)\n\n def forward(self, x):\n c = self.conv_transpose(x)\n N, C, D, H, W = c.shape\n S = D * H * W\n c2 = c.contiguous().view(N * C, S)\n\n ssum = torch.empty(N * C, device=c.device, dtype=torch.float32)\n ssq = torch.empty(N * C, device=c.device, dtype=torch.float32)\n reduce_kernel[(N * C,)](c2, ssum, ssq, S, BLOCK=1024)\n\n ssum_nc = ssum.view(N, C)\n ssq_nc = ssq.view(N, C)\n M = N * S\n mean_c = ssum_nc.sum(0) / M\n var_c = ssq_nc.sum(0) / M - mean_c * mean_c\n scale_c = self.batch_norm.weight / torch.sqrt(var_c + self.batch_norm.eps)\n shift_c = self.batch_norm.bias - scale_c * mean_c\n\n OD = D // 4\n OH = H // 4\n OW = W // 4\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=torch.float32)\n total = N * C * OD * OH * OW\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n cc = c.contiguous()\n pool_kernel[grid](cc, out, scale_c.contiguous(), shift_c.contiguous(),\n N, C, D, H, W, OD, OH, OW, BLOCK=BLOCK)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 12888, "ctx_sha": "10c1ea8230b0eef6", "names_self": false, "family": "conv_transpose", "level": 2, "name": "ConvTranspose3d_LayerNorm_GELU_Scaling", "instruction": "KernelBench level 2 problem L2_034 (ConvTranspose3d_LayerNorm_GELU_Scaling), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Model that performs a 3D transposed convolution, layer normalization, GELU activation, and scaling.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, bias=True, eps=1e-5, scaling_factor=1.0):\n super(Model, self).__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, bias=bias)\n self.layer_norm = nn.LayerNorm(out_channels, eps=eps)\n self.scaling_factor = scaling_factor\n\n def forward(self, x):\n \"\"\"\n Args:\n x (torch.Tensor): Input tensor of shape (batch_size, in_channels, D, H, W).\n\n Returns:\n torch.Tensor: Output tensor of shape (batch_size, out_channels, D', H', W').\n \"\"\"\n x = self.conv_transpose(x)\n x = self.layer_norm(x)\n x = torch.nn.functional.gelu(x)\n x = x * self.scaling_factor\n return x\n\nbatch_size = 32\nin_channels = 32\nout_channels = 64\nD, H, W = 16, 32, 32\nkernel_size = 4\nstride = 2\npadding = 1\nbias = True\neps = 1e-5\nscaling_factor = 1.0\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, D, H, W)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, stride, padding, bias, eps, scaling_factor]```\n"}, "L2_060": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_089 ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max, 1.06x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, sub_ptr, out_ptr, N, C, S, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n mask = idx < total\n\n # idx indexes (n, s) flat where s in [0,S)\n n = idx // S\n s = idx % S\n base = n * C * S + s\n\n # pass 1: max over channels\n mx = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=-1e30)\n mx = tl.maximum(mx, v)\n\n # pass 2: sum of exp\n sm = tl.zeros((BLOCK,), tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sm += tl.exp(v - mx)\n\n # pass 3: softmax, subtract, swish, max over channels\n res = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sub = tl.load(sub_ptr + c)\n sm_val = tl.exp(v - mx) / sm\n y = sm_val - sub\n swish = (tl.sigmoid(y) * y)\n res = tl.maximum(res, swish)\n\n tl.store(out_ptr + idx, res, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, pool_kernel_size, pool_stride, pool_padding):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.max_pool = nn.MaxPool3d(kernel_size=pool_kernel_size, stride=pool_stride, padding=pool_padding)\n self.subtract = nn.Parameter(torch.randn(out_channels))\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = self.max_pool(x).contiguous()\n N, C, D, H, W = x.shape\n S = D * H * W\n total = N * S\n\n out = torch.empty((N, D, H, W), device=x.device, dtype=x.dtype)\n sub = self.subtract.contiguous()\n\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n fused_kernel[grid](x, sub, out, N, C, S, total, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_072 ConvTranspose3d_BatchNorm_AvgPool_AvgPool, 1.68x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef reduce_kernel(x_ptr, sum_ptr, sqsum_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = tl.arange(0, BLOCK)\n base = pid * S\n acc = tl.zeros((), dtype=tl.float32)\n accsq = tl.zeros((), dtype=tl.float32)\n for i in range(0, S, BLOCK):\n idx = i + offs\n m = idx < S\n v = tl.load(x_ptr + base + idx, mask=m, other=0.0)\n acc += tl.sum(v)\n accsq += tl.sum(v * v)\n tl.store(sum_ptr + pid, acc)\n tl.store(sqsum_ptr + pid, accsq)\n\n\n@triton.jit\ndef pool_kernel(x_ptr, out_ptr, scale_ptr, shift_ptr,\n N, C, D, H, W, OD, OH, OW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * OD * OH * OW\n mask = offs < total\n o = offs.to(tl.int64)\n ow = o % OW\n t = o // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n t = t // OD\n c = t % C\n n = t // C\n\n sc = tl.load(scale_ptr + c, mask=mask, other=0.0)\n sh = tl.load(shift_ptr + c, mask=mask, other=0.0)\n\n HW = H * W\n DHW = D * HW\n base = (n * C + c) * DHW\n\n acc = tl.zeros((BLOCK,), dtype=tl.float32)\n for dd in tl.static_range(4):\n for hh in tl.static_range(4):\n for ww in tl.static_range(4):\n id_ = od * 4 + dd\n ih = oh * 4 + hh\n iw = ow * 4 + ww\n addr = base + id_ * HW + ih * W + iw\n v = tl.load(x_ptr + addr, mask=mask, other=0.0)\n acc += v\n acc = acc * (1.0 / 64.0)\n r = sc * acc + sh\n tl.store(out_ptr + offs, r, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, bias_shape):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.batch_norm = nn.BatchNorm3d(out_channels)\n\n def forward(self, x):\n c = self.conv_transpose(x)\n N, C, D, H, W = c.shape\n S = D * H * W\n c2 = c.contiguous().view(N * C, S)\n\n ssum = torch.empty(N * C, device=c.device, dtype=torch.float32)\n ssq = torch.empty(N * C, device=c.device, dtype=torch.float32)\n reduce_kernel[(N * C,)](c2, ssum, ssq, S, BLOCK=1024)\n\n ssum_nc = ssum.view(N, C)\n ssq_nc = ssq.view(N, C)\n M = N * S\n mean_c = ssum_nc.sum(0) / M\n var_c = ssq_nc.sum(0) / M - mean_c * mean_c\n scale_c = self.batch_norm.weight / torch.sqrt(var_c + self.batch_norm.eps)\n shift_c = self.batch_norm.bias - scale_c * mean_c\n\n OD = D // 4\n OH = H // 4\n OW = W // 4\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=torch.float32)\n total = N * C * OD * OH * OW\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n cc = c.contiguous()\n pool_kernel[grid](cc, out, scale_c.contiguous(), shift_c.contiguous(),\n N, C, D, H, W, OD, OH, OW, BLOCK=BLOCK)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_089 ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max, 1.06x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, sub_ptr, out_ptr, N, C, S, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n mask = idx < total\n\n # idx indexes (n, s) flat where s in [0,S)\n n = idx // S\n s = idx % S\n base = n * C * S + s\n\n # pass 1: max over channels\n mx = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=-1e30)\n mx = tl.maximum(mx, v)\n\n # pass 2: sum of exp\n sm = tl.zeros((BLOCK,), tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sm += tl.exp(v - mx)\n\n # pass 3: softmax, subtract, swish, max over channels\n res = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sub = tl.load(sub_ptr + c)\n sm_val = tl.exp(v - mx) / sm\n y = sm_val - sub\n swish = (tl.sigmoid(y) * y)\n res = tl.maximum(res, swish)\n\n tl.store(out_ptr + idx, res, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, pool_kernel_size, pool_stride, pool_padding):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.max_pool = nn.MaxPool3d(kernel_size=pool_kernel_size, stride=pool_stride, padding=pool_padding)\n self.subtract = nn.Parameter(torch.randn(out_channels))\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = self.max_pool(x).contiguous()\n N, C, D, H, W = x.shape\n S = D * H * W\n total = N * S\n\n out = torch.empty((N, D, H, W), device=x.device, dtype=x.dtype)\n sub = self.subtract.contiguous()\n\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n fused_kernel[grid](x, sub, out, N, C, S, total, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_072 ConvTranspose3d_BatchNorm_AvgPool_AvgPool, 1.68x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef reduce_kernel(x_ptr, sum_ptr, sqsum_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = tl.arange(0, BLOCK)\n base = pid * S\n acc = tl.zeros((), dtype=tl.float32)\n accsq = tl.zeros((), dtype=tl.float32)\n for i in range(0, S, BLOCK):\n idx = i + offs\n m = idx < S\n v = tl.load(x_ptr + base + idx, mask=m, other=0.0)\n acc += tl.sum(v)\n accsq += tl.sum(v * v)\n tl.store(sum_ptr + pid, acc)\n tl.store(sqsum_ptr + pid, accsq)\n\n\n@triton.jit\ndef pool_kernel(x_ptr, out_ptr, scale_ptr, shift_ptr,\n N, C, D, H, W, OD, OH, OW, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * OD * OH * OW\n mask = offs < total\n o = offs.to(tl.int64)\n ow = o % OW\n t = o // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n t = t // OD\n c = t % C\n n = t // C\n\n sc = tl.load(scale_ptr + c, mask=mask, other=0.0)\n sh = tl.load(shift_ptr + c, mask=mask, other=0.0)\n\n HW = H * W\n DHW = D * HW\n base = (n * C + c) * DHW\n\n acc = tl.zeros((BLOCK,), dtype=tl.float32)\n for dd in tl.static_range(4):\n for hh in tl.static_range(4):\n for ww in tl.static_range(4):\n id_ = od * 4 + dd\n ih = oh * 4 + hh\n iw = ow * 4 + ww\n addr = base + id_ * HW + ih * W + iw\n v = tl.load(x_ptr + addr, mask=mask, other=0.0)\n acc += v\n acc = acc * (1.0 / 64.0)\n r = sc * acc + sh\n tl.store(out_ptr + offs, r, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, bias_shape):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.batch_norm = nn.BatchNorm3d(out_channels)\n\n def forward(self, x):\n c = self.conv_transpose(x)\n N, C, D, H, W = c.shape\n S = D * H * W\n c2 = c.contiguous().view(N * C, S)\n\n ssum = torch.empty(N * C, device=c.device, dtype=torch.float32)\n ssq = torch.empty(N * C, device=c.device, dtype=torch.float32)\n reduce_kernel[(N * C,)](c2, ssum, ssq, S, BLOCK=1024)\n\n ssum_nc = ssum.view(N, C)\n ssq_nc = ssq.view(N, C)\n M = N * S\n mean_c = ssum_nc.sum(0) / M\n var_c = ssq_nc.sum(0) / M - mean_c * mean_c\n scale_c = self.batch_norm.weight / torch.sqrt(var_c + self.batch_norm.eps)\n shift_c = self.batch_norm.bias - scale_c * mean_c\n\n OD = D // 4\n OH = H // 4\n OW = W // 4\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=torch.float32)\n total = N * C * OD * OH * OW\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n cc = c.contiguous()\n pool_kernel[grid](cc, out, scale_c.contiguous(), shift_c.contiguous(),\n N, C, D, H, W, OD, OH, OW, BLOCK=BLOCK)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 12155, "ctx_sha": "1323e4e600b1300c", "names_self": false, "family": "conv_transpose", "level": 2, "name": "ConvTranspose3d_Swish_GroupNorm_HardSwish", "instruction": "KernelBench level 2 problem L2_060 (ConvTranspose3d_Swish_GroupNorm_HardSwish), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Model that performs a 3D transposed convolution, applies Swish activation, \n group normalization, and then HardSwish activation.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, groups, eps, bias=True):\n super(Model, self).__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, bias=bias)\n self.group_norm = nn.GroupNorm(num_groups=groups, num_channels=out_channels, eps=eps)\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = torch.sigmoid(x) * x # Swish activation\n x = self.group_norm(x)\n x = torch.nn.functional.hardswish(x) # HardSwish activation\n return x\n\nbatch_size = 128\nin_channels = 3\nout_channels = 16\ndepth, height, width = 16, 32, 32\nkernel_size = 3\nstride = 2\npadding = 1\ngroups = 4\neps = 1e-5\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, depth, height, width)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, stride, padding, groups, eps]```\n"}, "L2_091": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_011 ConvTranspose2d_BatchNorm_Tanh_MaxPool_GroupNorm, 1.05x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef reduce_nc(x_ptr, sum_ptr, sq_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = tl.arange(0, BLOCK)\n base = pid * S\n acc = tl.zeros((), dtype=tl.float32)\n accsq = tl.zeros((), dtype=tl.float32)\n for i in range(0, S, BLOCK):\n idx = i + offs\n m = idx < S\n v = tl.load(x_ptr + base + idx, mask=m, other=0.0)\n acc += tl.sum(v)\n accsq += tl.sum(v * v)\n tl.store(sum_ptr + pid, acc)\n tl.store(sq_ptr + pid, accsq)\n\n\n@triton.jit\ndef bn_tanh_pool(x_ptr, out_ptr, scale_ptr, shift_ptr,\n N, C, H, W, Ho, Wo, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * Ho * Wo\n m = offs < total\n wo = offs % Wo\n t = offs // Wo\n ho = t % Ho\n t = t // Ho\n c = t % C\n n = t // C\n\n sc = tl.load(scale_ptr + c, mask=m, other=0.0)\n sh = tl.load(shift_ptr + c, mask=m, other=0.0)\n\n hbase = ho * 2\n wbase = wo * 2\n inbase = ((n * C + c) * H + hbase) * W + wbase\n\n v00 = tl.load(x_ptr + inbase, mask=m, other=-1e30)\n v01 = tl.load(x_ptr + inbase + 1, mask=m, other=-1e30)\n v10 = tl.load(x_ptr + inbase + W, mask=m, other=-1e30)\n v11 = tl.load(x_ptr + inbase + W + 1, mask=m, other=-1e30)\n\n t00 = tl.extra.cuda.libdevice.tanh(sc * v00 + sh)\n t01 = tl.extra.cuda.libdevice.tanh(sc * v01 + sh)\n t10 = tl.extra.cuda.libdevice.tanh(sc * v10 + sh)\n t11 = tl.extra.cuda.libdevice.tanh(sc * v11 + sh)\n\n mx = tl.maximum(tl.maximum(t00, t01), tl.maximum(t10, t11))\n tl.store(out_ptr + offs, mx, mask=m)\n\n\n@triton.jit\ndef gn_apply(y_ptr, out_ptr, mean_ptr, inv_ptr, w_ptr, b_ptr,\n N, C, So, cpg, GPC, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * So\n m = offs < total\n t = offs // So\n c = t % C\n n = t // C\n g = c // cpg\n ng = n * GPC + g\n\n mean = tl.load(mean_ptr + ng, mask=m, other=0.0)\n inv = tl.load(inv_ptr + ng, mask=m, other=0.0)\n w = tl.load(w_ptr + c, mask=m, other=0.0)\n b = tl.load(b_ptr + c, mask=m, other=0.0)\n v = tl.load(y_ptr + offs, mask=m, other=0.0)\n r = (v - mean) * inv * w + b\n tl.store(out_ptr + offs, r, mask=m)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, groups, num_groups):\n super(ModelNew, self).__init__()\n self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.batch_norm = nn.BatchNorm2d(out_channels)\n self.max_pool = nn.MaxPool2d(kernel_size=2, stride=2)\n self.group_norm = nn.GroupNorm(num_groups=num_groups, num_channels=out_channels)\n self.num_groups = num_groups\n\n def forward(self, x):\n c = self.conv_transpose(x)\n N, C, H, W = c.shape\n c = c.contiguous()\n S = H * W\n c2 = c.view(N * C, S)\n\n ssum = torch.empty(N * C, device=c.device, dtype=torch.float32)\n ssq = torch.empty(N * C, device=c.device, dtype=torch.float32)\n reduce_nc[(N * C,)](c2, ssum, ssq, S, BLOCK=1024)\n\n ssum = ssum.view(N, C)\n ssq = ssq.view(N, C)\n M = N * S\n mean_c = ssum.sum(0) / M\n var_c = ssq.sum(0) / M - mean_c * mean_c\n scale_c = (self.batch_norm.weight / torch.sqrt(var_c + self.batch_norm.eps)).contiguous()\n shift_c = (self.batch_norm.bias - mean_c * scale_c).contiguous()\n\n Ho = H // 2\n Wo = W // 2\n y = torch.empty(N, C, Ho, Wo, device=c.device, dtype=torch.float32)\n total = N * C * Ho * Wo\n grid = ((total + 255) // 256,)\n bn_tanh_pool[grid](c, y, scale_c, shift_c, N, C, H, W, Ho, Wo, BLOCK=256)\n\n # group norm\n G = self.num_groups\n cpg = C // G\n So = Ho * Wo\n seg = cpg * So\n yv = y.view(N * G, seg)\n gsum = torch.empty(N * G, device=c.device, dtype=torch.float32)\n gsq = torch.empty(N * G, device=c.device, dtype=torch.float32)\n reduce_nc[(N * G,)](yv, gsum, gsq, seg, BLOCK=1024)\n gmean = gsum / seg\n gvar = gsq / seg - gmean * gmean\n ginv = 1.0 / torch.sqrt(gvar + self.group_norm.eps)\n\n out = torch.empty_like(y)\n totalg = N * C * So\n gridg = ((totalg + 255) // 256,)\n gn_apply[gridg](y, out, gmean.contiguous(), ginv.contiguous(),\n self.group_norm.weight.contiguous(), self.group_norm.bias.contiguous(),\n N, C, So, cpg, G, BLOCK=256)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_089 ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max, 1.06x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, sub_ptr, out_ptr, N, C, S, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n mask = idx < total\n\n # idx indexes (n, s) flat where s in [0,S)\n n = idx // S\n s = idx % S\n base = n * C * S + s\n\n # pass 1: max over channels\n mx = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=-1e30)\n mx = tl.maximum(mx, v)\n\n # pass 2: sum of exp\n sm = tl.zeros((BLOCK,), tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sm += tl.exp(v - mx)\n\n # pass 3: softmax, subtract, swish, max over channels\n res = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sub = tl.load(sub_ptr + c)\n sm_val = tl.exp(v - mx) / sm\n y = sm_val - sub\n swish = (tl.sigmoid(y) * y)\n res = tl.maximum(res, swish)\n\n tl.store(out_ptr + idx, res, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, pool_kernel_size, pool_stride, pool_padding):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.max_pool = nn.MaxPool3d(kernel_size=pool_kernel_size, stride=pool_stride, padding=pool_padding)\n self.subtract = nn.Parameter(torch.randn(out_channels))\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = self.max_pool(x).contiguous()\n N, C, D, H, W = x.shape\n S = D * H * W\n total = N * S\n\n out = torch.empty((N, D, H, W), device=x.device, dtype=x.dtype)\n sub = self.subtract.contiguous()\n\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n fused_kernel[grid](x, sub, out, N, C, S, total, BLOCK=BLOCK)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_011 ConvTranspose2d_BatchNorm_Tanh_MaxPool_GroupNorm, 1.05x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef reduce_nc(x_ptr, sum_ptr, sq_ptr, S, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = tl.arange(0, BLOCK)\n base = pid * S\n acc = tl.zeros((), dtype=tl.float32)\n accsq = tl.zeros((), dtype=tl.float32)\n for i in range(0, S, BLOCK):\n idx = i + offs\n m = idx < S\n v = tl.load(x_ptr + base + idx, mask=m, other=0.0)\n acc += tl.sum(v)\n accsq += tl.sum(v * v)\n tl.store(sum_ptr + pid, acc)\n tl.store(sq_ptr + pid, accsq)\n\n\n@triton.jit\ndef bn_tanh_pool(x_ptr, out_ptr, scale_ptr, shift_ptr,\n N, C, H, W, Ho, Wo, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * Ho * Wo\n m = offs < total\n wo = offs % Wo\n t = offs // Wo\n ho = t % Ho\n t = t // Ho\n c = t % C\n n = t // C\n\n sc = tl.load(scale_ptr + c, mask=m, other=0.0)\n sh = tl.load(shift_ptr + c, mask=m, other=0.0)\n\n hbase = ho * 2\n wbase = wo * 2\n inbase = ((n * C + c) * H + hbase) * W + wbase\n\n v00 = tl.load(x_ptr + inbase, mask=m, other=-1e30)\n v01 = tl.load(x_ptr + inbase + 1, mask=m, other=-1e30)\n v10 = tl.load(x_ptr + inbase + W, mask=m, other=-1e30)\n v11 = tl.load(x_ptr + inbase + W + 1, mask=m, other=-1e30)\n\n t00 = tl.extra.cuda.libdevice.tanh(sc * v00 + sh)\n t01 = tl.extra.cuda.libdevice.tanh(sc * v01 + sh)\n t10 = tl.extra.cuda.libdevice.tanh(sc * v10 + sh)\n t11 = tl.extra.cuda.libdevice.tanh(sc * v11 + sh)\n\n mx = tl.maximum(tl.maximum(t00, t01), tl.maximum(t10, t11))\n tl.store(out_ptr + offs, mx, mask=m)\n\n\n@triton.jit\ndef gn_apply(y_ptr, out_ptr, mean_ptr, inv_ptr, w_ptr, b_ptr,\n N, C, So, cpg, GPC, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n total = N * C * So\n m = offs < total\n t = offs // So\n c = t % C\n n = t // C\n g = c // cpg\n ng = n * GPC + g\n\n mean = tl.load(mean_ptr + ng, mask=m, other=0.0)\n inv = tl.load(inv_ptr + ng, mask=m, other=0.0)\n w = tl.load(w_ptr + c, mask=m, other=0.0)\n b = tl.load(b_ptr + c, mask=m, other=0.0)\n v = tl.load(y_ptr + offs, mask=m, other=0.0)\n r = (v - mean) * inv * w + b\n tl.store(out_ptr + offs, r, mask=m)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, groups, num_groups):\n super(ModelNew, self).__init__()\n self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)\n self.batch_norm = nn.BatchNorm2d(out_channels)\n self.max_pool = nn.MaxPool2d(kernel_size=2, stride=2)\n self.group_norm = nn.GroupNorm(num_groups=num_groups, num_channels=out_channels)\n self.num_groups = num_groups\n\n def forward(self, x):\n c = self.conv_transpose(x)\n N, C, H, W = c.shape\n c = c.contiguous()\n S = H * W\n c2 = c.view(N * C, S)\n\n ssum = torch.empty(N * C, device=c.device, dtype=torch.float32)\n ssq = torch.empty(N * C, device=c.device, dtype=torch.float32)\n reduce_nc[(N * C,)](c2, ssum, ssq, S, BLOCK=1024)\n\n ssum = ssum.view(N, C)\n ssq = ssq.view(N, C)\n M = N * S\n mean_c = ssum.sum(0) / M\n var_c = ssq.sum(0) / M - mean_c * mean_c\n scale_c = (self.batch_norm.weight / torch.sqrt(var_c + self.batch_norm.eps)).contiguous()\n shift_c = (self.batch_norm.bias - mean_c * scale_c).contiguous()\n\n Ho = H // 2\n Wo = W // 2\n y = torch.empty(N, C, Ho, Wo, device=c.device, dtype=torch.float32)\n total = N * C * Ho * Wo\n grid = ((total + 255) // 256,)\n bn_tanh_pool[grid](c, y, scale_c, shift_c, N, C, H, W, Ho, Wo, BLOCK=256)\n\n # group norm\n G = self.num_groups\n cpg = C // G\n So = Ho * Wo\n seg = cpg * So\n yv = y.view(N * G, seg)\n gsum = torch.empty(N * G, device=c.device, dtype=torch.float32)\n gsq = torch.empty(N * G, device=c.device, dtype=torch.float32)\n reduce_nc[(N * G,)](yv, gsum, gsq, seg, BLOCK=1024)\n gmean = gsum / seg\n gvar = gsq / seg - gmean * gmean\n ginv = 1.0 / torch.sqrt(gvar + self.group_norm.eps)\n\n out = torch.empty_like(y)\n totalg = N * C * So\n gridg = ((totalg + 255) // 256,)\n gn_apply[gridg](y, out, gmean.contiguous(), ginv.contiguous(),\n self.group_norm.weight.contiguous(), self.group_norm.bias.contiguous(),\n N, C, So, cpg, G, BLOCK=256)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_089 ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max, 1.06x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, sub_ptr, out_ptr, N, C, S, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n mask = idx < total\n\n # idx indexes (n, s) flat where s in [0,S)\n n = idx // S\n s = idx % S\n base = n * C * S + s\n\n # pass 1: max over channels\n mx = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=-1e30)\n mx = tl.maximum(mx, v)\n\n # pass 2: sum of exp\n sm = tl.zeros((BLOCK,), tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sm += tl.exp(v - mx)\n\n # pass 3: softmax, subtract, swish, max over channels\n res = tl.full((BLOCK,), -1e30, tl.float32)\n for c in range(0, C):\n v = tl.load(x_ptr + base + c * S, mask=mask, other=0.0)\n sub = tl.load(sub_ptr + c)\n sm_val = tl.exp(v - mx) / sm\n y = sm_val - sub\n swish = (tl.sigmoid(y) * y)\n res = tl.maximum(res, swish)\n\n tl.store(out_ptr + idx, res, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, pool_kernel_size, pool_stride, pool_padding):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.max_pool = nn.MaxPool3d(kernel_size=pool_kernel_size, stride=pool_stride, padding=pool_padding)\n self.subtract = nn.Parameter(torch.randn(out_channels))\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = self.max_pool(x).contiguous()\n N, C, D, H, W = x.shape\n S = D * H * W\n total = N * S\n\n out = torch.empty((N, D, H, W), device=x.device, dtype=x.dtype)\n sub = self.subtract.contiguous()\n\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n fused_kernel[grid](x, sub, out, N, C, S, total, BLOCK=BLOCK)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 13707, "ctx_sha": "c2fd2e75f0a9c4ac", "names_self": false, "family": "conv_transpose", "level": 2, "name": "ConvTranspose2d_Softmax_BiasAdd_Scaling_Sigmoid", "instruction": "KernelBench level 2 problem L2_091 (ConvTranspose2d_Softmax_BiasAdd_Scaling_Sigmoid), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Model that performs a transposed convolution, applies softmax, adds a bias term, scales the result, and applies sigmoid.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, bias_shape, scaling_factor):\n super(Model, self).__init__()\n self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.bias = nn.Parameter(torch.randn(bias_shape)) \n self.scaling_factor = scaling_factor\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = torch.softmax(x, dim=1)\n x = x + self.bias\n x = x * self.scaling_factor\n x = torch.sigmoid(x)\n return x\n\nbatch_size = 128\nin_channels = 64\nout_channels = 128\nheight, width = 64, 64\nkernel_size = 4\nstride = 2\npadding = 1\noutput_padding = 1\nbias_shape = (out_channels, 1, 1)\nscaling_factor = 2.0\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, height, width)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, stride, padding, output_padding, bias_shape, scaling_factor]```\n"}, "L2_093": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_074 ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max, 1.26x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, out_ptr, mult_ptr, N, C, D, H, W, OD, OH, OW,\n slope, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n mask = idx < total\n\n ow = idx % OW\n t = idx // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n nc = t // OD\n c = nc % C\n\n m = tl.load(mult_ptr + c, mask=mask, other=0.0)\n\n acc = tl.full((BLOCK,), -1e30, tl.float32)\n for dz in tl.static_range(2):\n for dy in tl.static_range(2):\n for dx in tl.static_range(2):\n iz = od * 2 + dz\n iy = oh * 2 + dy\n ix = ow * 2 + dx\n in_off = (((nc * D + iz) * H + iy) * W + ix)\n v = tl.load(x_ptr + in_off, mask=mask, other=0.0)\n v = tl.where(v >= 0, v, v * slope)\n v = v * m\n v = tl.where(v >= 0, v, v * slope)\n acc = tl.maximum(acc, v)\n tl.store(out_ptr + idx, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, multiplier_shape):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.multiplier = nn.Parameter(torch.randn(multiplier_shape))\n\n def forward(self, x):\n c = self.conv_transpose(x).contiguous()\n N, C, D, H, W = c.shape\n OD, OH, OW = D // 2, H // 2, W // 2\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=c.dtype)\n total = N * C * OD * OH * OW\n mult = self.multiplier.contiguous().view(-1)\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n fused_kernel[grid](c, out, mult, N, C, D, H, W, OD, OH, OW, 0.2, total, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_003 ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU, 1.26x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef ln_kernel(x_ptr, out_ptr, w_ptr, b_ptr, sw, W, eps, BLOCK: tl.constexpr):\n pid = tl.program_id(0).to(tl.int64)\n offs = tl.arange(0, BLOCK)\n m = offs < W\n base = pid * W\n v = tl.load(x_ptr + base + offs, mask=m, other=0.0) + sw\n mean = tl.sum(v, axis=0) / W\n d = tl.where(m, v - mean, 0.0)\n var = tl.sum(d * d, axis=0) / W\n rstd = 1.0 / tl.sqrt(var + eps)\n w = tl.load(w_ptr + offs, mask=m, other=0.0)\n b = tl.load(b_ptr + offs, mask=m, other=0.0)\n r = d * rstd * w + b\n tl.store(out_ptr + base + offs, r, mask=m)\n\n\n@triton.jit\ndef pool_gelu_kernel(x_ptr, out_ptr, D, H, W, OD, OH, OW, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n idx64 = idx.to(tl.int64)\n mask = idx < total\n ow = idx64 % OW\n t = idx64 // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n nc = t // OD\n\n acc = tl.zeros((BLOCK,), tl.float32)\n for dz in tl.static_range(2):\n for dy in tl.static_range(2):\n for dx in tl.static_range(2):\n iz = od * 2 + dz\n iy = oh * 2 + dy\n ix = ow * 2 + dx\n in_off = ((nc * D + iz) * H + iy) * W + ix\n v = tl.load(x_ptr + in_off, mask=mask, other=0.0)\n acc += v\n acc = acc * 0.125\n gelu = acc * 0.5 * (1.0 + tl.erf(acc * 0.70710678118654752440))\n tl.store(out_ptr + idx64, gelu, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, sum_weight, norm_shape, pool_kernel_size):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.sum_weight = nn.Parameter(torch.tensor(sum_weight))\n self.norm = nn.LayerNorm(norm_shape)\n self.avg_pool = nn.AvgPool3d(kernel_size=pool_kernel_size)\n self.gelu = nn.GELU()\n\n def forward(self, x):\n c = self.conv_transpose(x).contiguous()\n N, C, D, H, W = c.shape\n rows = N * C * D * H\n c2 = c.view(rows, W)\n normed = torch.empty_like(c2)\n BLOCKW = triton.next_power_of_2(W)\n w = self.norm.weight.contiguous()\n b = self.norm.bias.contiguous()\n ln_kernel[(rows,)](c2, normed, w, b, float(self.sum_weight.item()), W, self.norm.eps, BLOCK=BLOCKW)\n normed = normed.view(N, C, D, H, W)\n\n OD, OH, OW = D // 2, H // 2, W // 2\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=c.dtype)\n total = N * C * OD * OH * OW\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n pool_gelu_kernel[grid](normed, out, D, H, W, OD, OH, OW, total, BLOCK=BLOCK)\n return out\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier conv_transpose problems (wrong results or slower than eager)\n- Pitfall: Avoid launching a per-forward weight-transform kernel (flip/transpose) before a library call. Cache the transformed weight once, or fuse the transform, since extra launches and memory traffic make it slower than eager.\n- Pitfall: Don'...'s native transposed conv is usually as fast or faster, so this measured slower.\n- Pitfall: In Triton kernels over large tensors (e.g. 3D conv outputs), compute offsets in int64 (cast program_id/indices with .to(tl.int64)). int32 products like n*C*S can overflow and crash, leaving no output during timing.\n- Pitfall: Never launch a pure copy/identity kernel into a fresh buffer just to have a custom kernel; that adds a full memory round-trip and guarantees slowdown versus eager.\n- Pitfall: Don't rewrite conv_transpose as flipped-weight F.conv2d plus a separate elementwise kernel; the per-call weight flip and extra full-output pass make it slower. Fuse bias into a real kernel, or skip pointless copies.\n\n### Verified recipes for conv_transpose problems (speedups measured by the protected evaluator)\n- [2.29x on conv_transposed_2D_asymmetric_input_asymmetric_kernel___padded__] For stride-1 transposed conv, rewrite it as a regular cuDNN conv2d: build the weight with a tiny Triton kernel that swaps the IC/OC axes and flips KH/KW, (IC,OC,KH,KW)->(OC,IC,KH-1-kh,KW-1-kw). Then call F.conv2d with padding=(K-1-p) per dimension and pass the bias through. cuDNN's forward conv path is much faster than ConvTranspose's dgrad path. Keep the math in fp32 so it is exact. For stride>1, groups, dilation or output_padding, fall back to nn.ConvTranspose2d. Cache the flipped weight if it is static.\n- [1.68x on ConvTranspose3d_BatchNorm_AvgPool_AvgPool] Keep the ConvTranspose in cuDNN via torch. Fold training-mode BatchNorm into a per-channel affine: one Triton program per (n,c) row loops over contiguous spatial data in 1024-wide blocks, accumulating fp32 sum and sum-of-squares. Finish mean/var/scale/shift with tiny torch ops. Because BN is affine, apply it after pooling: replace the two 2x pools with one fused 4x4x4 average kernel. Use one thread per output, int64 index math, static_range unrolled loads, and scale*avg+shift at store.\n- [1.32x on ConvTranspose3d_BatchNorm_Subtract] Keep ConvTranspose in cuDNN via torch. Fuse everything after it into two Triton passes over the contiguous (N*C, S) view. Pass 1: one program per (n,c) row, loop over S in 1024-element blocks, accumulate fp32 sum and sum-of-squares. Finish the tiny per-channel math in torch: batch mean/var (training-mode BN) and scale = gamma/sqrt(var+eps). Pass 2: write scale*(x - row_mean) in one read-modify-write sweep. BN's beta, shift and the conv bias cancel algebraically, so fold them away. fp32 accumulation meets 1e-4.\n- [1.26x on ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU] Keep ConvTranspose in cuDNN via torch and fuse only the epilogue in Triton. LayerNorm normalises the last dim (W), not channels, so treat the output as a 2D [rows, W] view. Launch one program per row with BLOCK=next_pow2(W), add scalar bias before the mean, take a two-pass variance in fp32, and compute rstd as 1/sqrt(var+eps). Then run a second elementwise kernel fusing avgpool (static_range window loads, multiply by 1/k) with exact erf-GELU. Use int64 index math. Better still, fuse LN into the pool kernel to avoid the intermediate write.\n- [1.26x on ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max] Keep the ConvTranspose3d itself in cuDNN via nn.ConvTranspose3d and fuse the entire epilogue into one Triton kernel that reads the conv output once: LeakyReLU, per-channel scale, LeakyReLU, MaxPool. Launch one thread per pooled output element over a flat index (BLOCK=256, 1D grid). Decode n\u00b7c/od/oh/ow with div/mod, load the per-channel multiplier once, and unroll the 2x2x2 window with tl.static_range. Use tl.where for the slopes and a -1e30 init for max. Keep all math fp32, which stays within 1e-4.\n- [1.06x on ConvTranspose3d_MaxPool_Softmax_Subtract_Swish_Max] Keep ConvTranspose3d (and MaxPool3d) in cuDNN via torch and call .contiguous() on the result. Fuse all channel-wise epilogues (softmax over C, per-channel bias/subtract, activation, reduction over C) into one Triton kernel. Map one lane per (n, spatial) position with a flat 1D grid and BLOCK=256. Loop over the C channels with stride-S loads, so consecutive lanes read consecutive spatial addresses (coalesced). Use a stable 3-pass softmax (max, sum-exp, normalize+epilogue) in fp32. Re-reads hit L1/L2. Write only the reduced output.\n\n### A verified kernel for a related conv_transpose problem (L2_074 ConvTranspose3d_LeakyReLU_Multiply_LeakyReLU_Max, 1.26x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef fused_kernel(x_ptr, out_ptr, mult_ptr, N, C, D, H, W, OD, OH, OW,\n slope, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n mask = idx < total\n\n ow = idx % OW\n t = idx // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n nc = t // OD\n c = nc % C\n\n m = tl.load(mult_ptr + c, mask=mask, other=0.0)\n\n acc = tl.full((BLOCK,), -1e30, tl.float32)\n for dz in tl.static_range(2):\n for dy in tl.static_range(2):\n for dx in tl.static_range(2):\n iz = od * 2 + dz\n iy = oh * 2 + dy\n ix = ow * 2 + dx\n in_off = (((nc * D + iz) * H + iy) * W + ix)\n v = tl.load(x_ptr + in_off, mask=mask, other=0.0)\n v = tl.where(v >= 0, v, v * slope)\n v = v * m\n v = tl.where(v >= 0, v, v * slope)\n acc = tl.maximum(acc, v)\n tl.store(out_ptr + idx, acc, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, multiplier_shape):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.multiplier = nn.Parameter(torch.randn(multiplier_shape))\n\n def forward(self, x):\n c = self.conv_transpose(x).contiguous()\n N, C, D, H, W = c.shape\n OD, OH, OW = D // 2, H // 2, W // 2\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=c.dtype)\n total = N * C * OD * OH * OW\n mult = self.multiplier.contiguous().view(-1)\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n fused_kernel[grid](c, out, mult, N, C, D, H, W, OD, OH, OW, 0.2, total, BLOCK=BLOCK)\n return out\n```\n\n### A verified kernel for a related conv_transpose problem (L2_003 ConvTranspose3d_Sum_LayerNorm_AvgPool_GELU, 1.26x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n\n@triton.jit\ndef ln_kernel(x_ptr, out_ptr, w_ptr, b_ptr, sw, W, eps, BLOCK: tl.constexpr):\n pid = tl.program_id(0).to(tl.int64)\n offs = tl.arange(0, BLOCK)\n m = offs < W\n base = pid * W\n v = tl.load(x_ptr + base + offs, mask=m, other=0.0) + sw\n mean = tl.sum(v, axis=0) / W\n d = tl.where(m, v - mean, 0.0)\n var = tl.sum(d * d, axis=0) / W\n rstd = 1.0 / tl.sqrt(var + eps)\n w = tl.load(w_ptr + offs, mask=m, other=0.0)\n b = tl.load(b_ptr + offs, mask=m, other=0.0)\n r = d * rstd * w + b\n tl.store(out_ptr + base + offs, r, mask=m)\n\n\n@triton.jit\ndef pool_gelu_kernel(x_ptr, out_ptr, D, H, W, OD, OH, OW, total, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n idx = pid * BLOCK + tl.arange(0, BLOCK)\n idx64 = idx.to(tl.int64)\n mask = idx < total\n ow = idx64 % OW\n t = idx64 // OW\n oh = t % OH\n t = t // OH\n od = t % OD\n nc = t // OD\n\n acc = tl.zeros((BLOCK,), tl.float32)\n for dz in tl.static_range(2):\n for dy in tl.static_range(2):\n for dx in tl.static_range(2):\n iz = od * 2 + dz\n iy = oh * 2 + dy\n ix = ow * 2 + dx\n in_off = ((nc * D + iz) * H + iy) * W + ix\n v = tl.load(x_ptr + in_off, mask=mask, other=0.0)\n acc += v\n acc = acc * 0.125\n gelu = acc * 0.5 * (1.0 + tl.erf(acc * 0.70710678118654752440))\n tl.store(out_ptr + idx64, gelu, mask=mask)\n\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, sum_weight, norm_shape, pool_kernel_size):\n super().__init__()\n self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)\n self.sum_weight = nn.Parameter(torch.tensor(sum_weight))\n self.norm = nn.LayerNorm(norm_shape)\n self.avg_pool = nn.AvgPool3d(kernel_size=pool_kernel_size)\n self.gelu = nn.GELU()\n\n def forward(self, x):\n c = self.conv_transpose(x).contiguous()\n N, C, D, H, W = c.shape\n rows = N * C * D * H\n c2 = c.view(rows, W)\n normed = torch.empty_like(c2)\n BLOCKW = triton.next_power_of_2(W)\n w = self.norm.weight.contiguous()\n b = self.norm.bias.contiguous()\n ln_kernel[(rows,)](c2, normed, w, b, float(self.sum_weight.item()), W, self.norm.eps, BLOCK=BLOCKW)\n normed = normed.view(N, C, D, H, W)\n\n OD, OH, OW = D // 2, H // 2, W // 2\n out = torch.empty((N, C, OD, OH, OW), device=c.device, dtype=c.dtype)\n total = N * C * OD * OH * OW\n BLOCK = 256\n grid = (triton.cdiv(total, BLOCK),)\n pool_gelu_kernel[grid](normed, out, D, H, W, OD, OH, OW, total, BLOCK=BLOCK)\n return out\n```"}, "same_for_readers": true, "ctx_chars": 11755, "ctx_sha": "c9bcbb50b8ac09fd", "names_self": false, "family": "conv_transpose", "level": 2, "name": "ConvTranspose2d_Add_Min_GELU_Multiply", "instruction": "KernelBench level 2 problem L2_093 (ConvTranspose2d_Add_Min_GELU_Multiply), op family: conv_transpose.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\n\nclass Model(nn.Module):\n \"\"\"\n Model that performs a transposed convolution, adds a value, takes the minimum, applies GELU, and multiplies by a value.\n \"\"\"\n def __init__(self, in_channels, out_channels, kernel_size, stride, add_value, multiply_value):\n super(Model, self).__init__()\n self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride)\n self.add_value = add_value\n self.multiply_value = multiply_value\n\n def forward(self, x):\n x = self.conv_transpose(x)\n x = x + self.add_value\n x = torch.min(x, torch.tensor(0.0, device=x.device))\n x = torch.nn.functional.gelu(x)\n x = x * self.multiply_value\n return x\n\nbatch_size = 128\nin_channels = 64\nout_channels = 128\nheight, width = 64, 64\nkernel_size = 4\nstride = 2\nadd_value = 0.5\nmultiply_value = 2.0\n\ndef get_inputs():\n return [torch.rand(batch_size, in_channels, height, width)]\n\ndef get_init_inputs():\n return [in_channels, out_channels, kernel_size, stride, add_value, multiply_value]```\n"}, "L3_013": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier network problems (wrong results or slower than eager)\n- Pitfall: For per-channel affine ops on NCHW, launch a 2D grid (one program per N*C row, tiles over HW). Precompute per-channel scale/shift once, instead of per-element div/mod, four parameter gathers and an rsqrt.\n- Pitfall: Don't replace cuDNN BatchNorm in training mode with separate torch mean/var reductions, running-stat updates and an elementwise kernel. The extra launches and memory passes outweigh the fusion; it ran far slower than eager.\n- Pitfall: Do not cache derived weights or folded parameters on the first forward call. Recompute them from the live parameters, or confirm that both modes match the reference within 1e-4.\n- Pitfall: Do not fold BatchNorm into conv weights using running_mean/var. The evaluator may run the reference in training mode, where BN normalizes with batch statistics. Check self.training, or compute batch stats yourself.\n\n### Verified recipes for network problems (speedups measured by the protected evaluator)\n- [1.00x on RegNet] Keep convolutions, pooling and Linear in cuDNN/cuBLAS via torch. Fuse BatchNorm+ReLU into one elementwise Triton kernel. Precompute per-channel scale=w/sqrt(var+eps) and shift=b-mean*scale in torch. In training mode use batch mean/var (unbiased=False) and update running stats with the unbiased correction n/(n-1). Index channels with (offs//HW)%C on contiguous NCHW, use 1D BLOCK=1024 with masking, and do fp32 math throughout. Gains are small (~1.005x). For more, fuse BN+ReLU+maxpool or the final pool with GAP.\n\n### A verified kernel for a related network problem (L3_027 RegNet, 1.00x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n@triton.jit\ndef bn_relu_kernel(x_ptr, out_ptr, scale_ptr, shift_ptr, HW, C, n_elem, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < n_elem\n c = (offs // HW) % C\n x = tl.load(x_ptr + offs, mask=mask, other=0.0)\n s = tl.load(scale_ptr + c, mask=mask, other=0.0)\n sh = tl.load(shift_ptr + c, mask=mask, other=0.0)\n y = x * s + sh\n y = tl.maximum(y, 0.0)\n tl.store(out_ptr + offs, y, mask=mask)\n\ndef apply_bn_relu(x, scale, shift):\n N, C, H, W = x.shape\n out = torch.empty_like(x)\n HW = H * W\n n = x.numel()\n grid = (triton.cdiv(n, 1024),)\n bn_relu_kernel[grid](x, out, scale.contiguous(), shift.contiguous(), HW, C, n, BLOCK=1024)\n return out\n\nclass ModelNew(nn.Module):\n def __init__(self, input_channels, stages, block_widths, output_classes):\n super(ModelNew, self).__init__()\n self.stages = stages\n self.block_widths = block_widths\n layers = []\n current = input_channels\n for i in range(stages):\n layers.append(nn.Sequential(\n nn.Conv2d(current, block_widths[i], kernel_size=3, padding=1),\n nn.BatchNorm2d(block_widths[i]),\n nn.ReLU(),\n nn.Conv2d(block_widths[i], block_widths[i], kernel_size=3, padding=1),\n nn.BatchNorm2d(block_widths[i]),\n nn.ReLU(),\n nn.MaxPool2d(kernel_size=2, stride=2),\n ))\n current = block_widths[i]\n self.feature_extractor = nn.Sequential(*layers)\n self.fc = nn.Linear(block_widths[-1], output_classes)\n\n def _bn_params(self, bn, x):\n if self.training:\n mean = x.mean(dim=[0, 2, 3])\n var = x.var(dim=[0, 2, 3], unbiased=False)\n n = x.numel() // x.shape[1]\n with torch.no_grad():\n bn.running_mean.mul_(1 - bn.momentum).add_(bn.momentum * mean)\n bn.running_var.mul_(1 - bn.momentum).add_(bn.momentum * var * n / (n - 1))\n else:\n mean = bn.running_mean\n var = bn.running_var\n scale = bn.weight / torch.sqrt(var + bn.eps)\n shift = bn.bias - mean * scale\n return scale, shift\n\n def forward(self, x):\n for stage in self.feature_extractor:\n conv1 = stage[0]\n bn1 = stage[1]\n conv2 = stage[3]\n bn2 = stage[4]\n pool = stage[6]\n x = conv1(x)\n s, sh = self._bn_params(bn1, x)\n x = apply_bn_relu(x, s, sh)\n x = conv2(x)\n s, sh = self._bn_params(bn2, x)\n x = apply_bn_relu(x, s, sh)\n x = pool(x)\n x = torch.mean(x, dim=[2, 3])\n x = self.fc(x)\n return x\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier network problems (wrong results or slower than eager)\n- Pitfall: For per-channel affine ops on NCHW, launch a 2D grid (one program per N*C row, tiles over HW). Precompute per-channel scale/shift once, instead of per-element div/mod, four parameter gathers and an rsqrt.\n- Pitfall: Don't replace cuDNN BatchNorm in training mode with separate torch mean/var reductions, running-stat updates and an elementwise kernel. The extra launches and memory passes outweigh the fusion; it ran far slower than eager.\n- Pitfall: Do not cache derived weights or folded parameters on the first forward call. Recompute them from the live parameters, or confirm that both modes match the reference within 1e-4.\n- Pitfall: Do not fold BatchNorm into conv weights using running_mean/var. The evaluator may run the reference in training mode, where BN normalizes with batch statistics. Check self.training, or compute batch stats yourself.\n\n### Verified recipes for network problems (speedups measured by the protected evaluator)\n- [1.00x on RegNet] Keep convolutions, pooling and Linear in cuDNN/cuBLAS via torch. Fuse BatchNorm+ReLU into one elementwise Triton kernel. Precompute per-channel scale=w/sqrt(var+eps) and shift=b-mean*scale in torch. In training mode use batch mean/var (unbiased=False) and update running stats with the unbiased correction n/(n-1). Index channels with (offs//HW)%C on contiguous NCHW, use 1D BLOCK=1024 with masking, and do fp32 math throughout. Gains are small (~1.005x). For more, fuse BN+ReLU+maxpool or the final pool with GAP.\n\n### A verified kernel for a related network problem (L3_027 RegNet, 1.00x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n@triton.jit\ndef bn_relu_kernel(x_ptr, out_ptr, scale_ptr, shift_ptr, HW, C, n_elem, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < n_elem\n c = (offs // HW) % C\n x = tl.load(x_ptr + offs, mask=mask, other=0.0)\n s = tl.load(scale_ptr + c, mask=mask, other=0.0)\n sh = tl.load(shift_ptr + c, mask=mask, other=0.0)\n y = x * s + sh\n y = tl.maximum(y, 0.0)\n tl.store(out_ptr + offs, y, mask=mask)\n\ndef apply_bn_relu(x, scale, shift):\n N, C, H, W = x.shape\n out = torch.empty_like(x)\n HW = H * W\n n = x.numel()\n grid = (triton.cdiv(n, 1024),)\n bn_relu_kernel[grid](x, out, scale.contiguous(), shift.contiguous(), HW, C, n, BLOCK=1024)\n return out\n\nclass ModelNew(nn.Module):\n def __init__(self, input_channels, stages, block_widths, output_classes):\n super(ModelNew, self).__init__()\n self.stages = stages\n self.block_widths = block_widths\n layers = []\n current = input_channels\n for i in range(stages):\n layers.append(nn.Sequential(\n nn.Conv2d(current, block_widths[i], kernel_size=3, padding=1),\n nn.BatchNorm2d(block_widths[i]),\n nn.ReLU(),\n nn.Conv2d(block_widths[i], block_widths[i], kernel_size=3, padding=1),\n nn.BatchNorm2d(block_widths[i]),\n nn.ReLU(),\n nn.MaxPool2d(kernel_size=2, stride=2),\n ))\n current = block_widths[i]\n self.feature_extractor = nn.Sequential(*layers)\n self.fc = nn.Linear(block_widths[-1], output_classes)\n\n def _bn_params(self, bn, x):\n if self.training:\n mean = x.mean(dim=[0, 2, 3])\n var = x.var(dim=[0, 2, 3], unbiased=False)\n n = x.numel() // x.shape[1]\n with torch.no_grad():\n bn.running_mean.mul_(1 - bn.momentum).add_(bn.momentum * mean)\n bn.running_var.mul_(1 - bn.momentum).add_(bn.momentum * var * n / (n - 1))\n else:\n mean = bn.running_mean\n var = bn.running_var\n scale = bn.weight / torch.sqrt(var + bn.eps)\n shift = bn.bias - mean * scale\n return scale, shift\n\n def forward(self, x):\n for stage in self.feature_extractor:\n conv1 = stage[0]\n bn1 = stage[1]\n conv2 = stage[3]\n bn2 = stage[4]\n pool = stage[6]\n x = conv1(x)\n s, sh = self._bn_params(bn1, x)\n x = apply_bn_relu(x, s, sh)\n x = conv2(x)\n s, sh = self._bn_params(bn2, x)\n x = apply_bn_relu(x, s, sh)\n x = pool(x)\n x = torch.mean(x, dim=[2, 3])\n x = self.fc(x)\n return x\n```"}, "same_for_readers": true, "ctx_chars": 6513, "ctx_sha": "1aa698d3a9589f25", "names_self": false, "family": "network", "level": 3, "name": "DenseNet121TransitionLayer", "instruction": "KernelBench level 3 problem L3_013 (DenseNet121TransitionLayer), op family: network.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\n\nclass Model(nn.Module):\n def __init__(self, num_input_features: int, num_output_features: int):\n \"\"\"\n :param num_input_features: The number of input feature maps\n :param num_output_features: The number of output feature maps\n \"\"\"\n super(Model, self).__init__()\n self.transition = nn.Sequential(\n nn.BatchNorm2d(num_input_features),\n nn.ReLU(inplace=True),\n nn.Conv2d(num_input_features, num_output_features, kernel_size=1, bias=False),\n nn.AvgPool2d(kernel_size=2, stride=2)\n )\n\n def forward(self, x):\n \"\"\"\n :param x: Input tensor of shape (batch_size, num_input_features, height, width)\n :return: Downsampled tensor with reduced number of feature maps\n \"\"\"\n return self.transition(x)\n\nbatch_size = 128\nnum_input_features = 32\nnum_output_features = 64\nheight, width = 256, 256\n\ndef get_inputs():\n return [torch.rand(batch_size, num_input_features, height, width)]\n\ndef get_init_inputs():\n return [num_input_features, num_output_features]\n```\n"}, "L3_025": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier network problems (wrong results or slower than eager)\n- Pitfall: For per-channel affine ops on NCHW, launch a 2D grid (one program per N*C row, tiles over HW). Precompute per-channel scale/shift once, instead of per-element div/mod, four parameter gathers and an rsqrt.\n- Pitfall: Don't replace cuDNN BatchNorm in training mode with separate torch mean/var reductions, running-stat updates and an elementwise kernel. The extra launches and memory passes outweigh the fusion; it ran far slower than eager.\n- Pitfall: Do not cache derived weights or folded parameters on the first forward call. Recompute them from the live parameters, or confirm that both modes match the reference within 1e-4.\n- Pitfall: Do not fold BatchNorm into conv weights using running_mean/var. The evaluator may run the reference in training mode, where BN normalizes with batch statistics. Check self.training, or compute batch stats yourself.\n\n### Verified recipes for network problems (speedups measured by the protected evaluator)\n- [1.00x on RegNet] Keep convolutions, pooling and Linear in cuDNN/cuBLAS via torch. Fuse BatchNorm+ReLU into one elementwise Triton kernel. Precompute per-channel scale=w/sqrt(var+eps) and shift=b-mean*scale in torch. In training mode use batch mean/var (unbiased=False) and update running stats with the unbiased correction n/(n-1). Index channels with (offs//HW)%C on contiguous NCHW, use 1D BLOCK=1024 with masking, and do fp32 math throughout. Gains are small (~1.005x). For more, fuse BN+ReLU+maxpool or the final pool with GAP.\n\n### A verified kernel for a related network problem (L3_027 RegNet, 1.00x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n@triton.jit\ndef bn_relu_kernel(x_ptr, out_ptr, scale_ptr, shift_ptr, HW, C, n_elem, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < n_elem\n c = (offs // HW) % C\n x = tl.load(x_ptr + offs, mask=mask, other=0.0)\n s = tl.load(scale_ptr + c, mask=mask, other=0.0)\n sh = tl.load(shift_ptr + c, mask=mask, other=0.0)\n y = x * s + sh\n y = tl.maximum(y, 0.0)\n tl.store(out_ptr + offs, y, mask=mask)\n\ndef apply_bn_relu(x, scale, shift):\n N, C, H, W = x.shape\n out = torch.empty_like(x)\n HW = H * W\n n = x.numel()\n grid = (triton.cdiv(n, 1024),)\n bn_relu_kernel[grid](x, out, scale.contiguous(), shift.contiguous(), HW, C, n, BLOCK=1024)\n return out\n\nclass ModelNew(nn.Module):\n def __init__(self, input_channels, stages, block_widths, output_classes):\n super(ModelNew, self).__init__()\n self.stages = stages\n self.block_widths = block_widths\n layers = []\n current = input_channels\n for i in range(stages):\n layers.append(nn.Sequential(\n nn.Conv2d(current, block_widths[i], kernel_size=3, padding=1),\n nn.BatchNorm2d(block_widths[i]),\n nn.ReLU(),\n nn.Conv2d(block_widths[i], block_widths[i], kernel_size=3, padding=1),\n nn.BatchNorm2d(block_widths[i]),\n nn.ReLU(),\n nn.MaxPool2d(kernel_size=2, stride=2),\n ))\n current = block_widths[i]\n self.feature_extractor = nn.Sequential(*layers)\n self.fc = nn.Linear(block_widths[-1], output_classes)\n\n def _bn_params(self, bn, x):\n if self.training:\n mean = x.mean(dim=[0, 2, 3])\n var = x.var(dim=[0, 2, 3], unbiased=False)\n n = x.numel() // x.shape[1]\n with torch.no_grad():\n bn.running_mean.mul_(1 - bn.momentum).add_(bn.momentum * mean)\n bn.running_var.mul_(1 - bn.momentum).add_(bn.momentum * var * n / (n - 1))\n else:\n mean = bn.running_mean\n var = bn.running_var\n scale = bn.weight / torch.sqrt(var + bn.eps)\n shift = bn.bias - mean * scale\n return scale, shift\n\n def forward(self, x):\n for stage in self.feature_extractor:\n conv1 = stage[0]\n bn1 = stage[1]\n conv2 = stage[3]\n bn2 = stage[4]\n pool = stage[6]\n x = conv1(x)\n s, sh = self._bn_params(bn1, x)\n x = apply_bn_relu(x, s, sh)\n x = conv2(x)\n s, sh = self._bn_params(bn2, x)\n x = apply_bn_relu(x, s, sh)\n x = pool(x)\n x = torch.mean(x, dim=[2, 3])\n x = self.fc(x)\n return x\n```", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier network problems (wrong results or slower than eager)\n- Pitfall: For per-channel affine ops on NCHW, launch a 2D grid (one program per N*C row, tiles over HW). Precompute per-channel scale/shift once, instead of per-element div/mod, four parameter gathers and an rsqrt.\n- Pitfall: Don't replace cuDNN BatchNorm in training mode with separate torch mean/var reductions, running-stat updates and an elementwise kernel. The extra launches and memory passes outweigh the fusion; it ran far slower than eager.\n- Pitfall: Do not cache derived weights or folded parameters on the first forward call. Recompute them from the live parameters, or confirm that both modes match the reference within 1e-4.\n- Pitfall: Do not fold BatchNorm into conv weights using running_mean/var. The evaluator may run the reference in training mode, where BN normalizes with batch statistics. Check self.training, or compute batch stats yourself.\n\n### Verified recipes for network problems (speedups measured by the protected evaluator)\n- [1.00x on RegNet] Keep convolutions, pooling and Linear in cuDNN/cuBLAS via torch. Fuse BatchNorm+ReLU into one elementwise Triton kernel. Precompute per-channel scale=w/sqrt(var+eps) and shift=b-mean*scale in torch. In training mode use batch mean/var (unbiased=False) and update running stats with the unbiased correction n/(n-1). Index channels with (offs//HW)%C on contiguous NCHW, use 1D BLOCK=1024 with masking, and do fp32 math throughout. Gains are small (~1.005x). For more, fuse BN+ReLU+maxpool or the final pool with GAP.\n\n### A verified kernel for a related network problem (L3_027 RegNet, 1.00x): adapt what applies\n```python\nimport torch\nimport torch.nn as nn\nimport triton\nimport triton.language as tl\n\n@triton.jit\ndef bn_relu_kernel(x_ptr, out_ptr, scale_ptr, shift_ptr, HW, C, n_elem, BLOCK: tl.constexpr):\n pid = tl.program_id(0)\n offs = pid * BLOCK + tl.arange(0, BLOCK)\n mask = offs < n_elem\n c = (offs // HW) % C\n x = tl.load(x_ptr + offs, mask=mask, other=0.0)\n s = tl.load(scale_ptr + c, mask=mask, other=0.0)\n sh = tl.load(shift_ptr + c, mask=mask, other=0.0)\n y = x * s + sh\n y = tl.maximum(y, 0.0)\n tl.store(out_ptr + offs, y, mask=mask)\n\ndef apply_bn_relu(x, scale, shift):\n N, C, H, W = x.shape\n out = torch.empty_like(x)\n HW = H * W\n n = x.numel()\n grid = (triton.cdiv(n, 1024),)\n bn_relu_kernel[grid](x, out, scale.contiguous(), shift.contiguous(), HW, C, n, BLOCK=1024)\n return out\n\nclass ModelNew(nn.Module):\n def __init__(self, input_channels, stages, block_widths, output_classes):\n super(ModelNew, self).__init__()\n self.stages = stages\n self.block_widths = block_widths\n layers = []\n current = input_channels\n for i in range(stages):\n layers.append(nn.Sequential(\n nn.Conv2d(current, block_widths[i], kernel_size=3, padding=1),\n nn.BatchNorm2d(block_widths[i]),\n nn.ReLU(),\n nn.Conv2d(block_widths[i], block_widths[i], kernel_size=3, padding=1),\n nn.BatchNorm2d(block_widths[i]),\n nn.ReLU(),\n nn.MaxPool2d(kernel_size=2, stride=2),\n ))\n current = block_widths[i]\n self.feature_extractor = nn.Sequential(*layers)\n self.fc = nn.Linear(block_widths[-1], output_classes)\n\n def _bn_params(self, bn, x):\n if self.training:\n mean = x.mean(dim=[0, 2, 3])\n var = x.var(dim=[0, 2, 3], unbiased=False)\n n = x.numel() // x.shape[1]\n with torch.no_grad():\n bn.running_mean.mul_(1 - bn.momentum).add_(bn.momentum * mean)\n bn.running_var.mul_(1 - bn.momentum).add_(bn.momentum * var * n / (n - 1))\n else:\n mean = bn.running_mean\n var = bn.running_var\n scale = bn.weight / torch.sqrt(var + bn.eps)\n shift = bn.bias - mean * scale\n return scale, shift\n\n def forward(self, x):\n for stage in self.feature_extractor:\n conv1 = stage[0]\n bn1 = stage[1]\n conv2 = stage[3]\n bn2 = stage[4]\n pool = stage[6]\n x = conv1(x)\n s, sh = self._bn_params(bn1, x)\n x = apply_bn_relu(x, s, sh)\n x = conv2(x)\n s, sh = self._bn_params(bn2, x)\n x = apply_bn_relu(x, s, sh)\n x = pool(x)\n x = torch.mean(x, dim=[2, 3])\n x = self.fc(x)\n return x\n```"}, "same_for_readers": true, "ctx_chars": 6513, "ctx_sha": "1aa698d3a9589f25", "names_self": false, "family": "network", "level": 3, "name": "ShuffleNetUnit", "instruction": "KernelBench level 3 problem L3_025 (ShuffleNetUnit), op family: network.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\n\nclass Model(nn.Module):\n def __init__(self, in_channels, out_channels, groups=3):\n \"\"\"\n ShuffleNet unit implementation.\n\n :param in_channels: Number of input channels.\n :param out_channels: Number of output channels.\n :param groups: Number of groups for group convolution.\n \"\"\"\n super(Model, self).__init__()\n \n # Ensure the output channels are divisible by groups\n assert out_channels % 4 == 0\n mid_channels = out_channels // 4\n \n # First 1x1 group convolution\n self.conv1 = nn.Conv2d(in_channels, mid_channels, kernel_size=1, stride=1, padding=0, groups=groups, bias=False)\n self.bn1 = nn.BatchNorm2d(mid_channels)\n \n # Depthwise 3x3 convolution\n self.conv2 = nn.Conv2d(mid_channels, mid_channels, kernel_size=3, stride=1, padding=1, groups=mid_channels, bias=False)\n self.bn2 = nn.BatchNorm2d(mid_channels)\n \n # Second 1x1 group convolution\n self.conv3 = nn.Conv2d(mid_channels, out_channels, kernel_size=1, stride=1, padding=0, groups=groups, bias=False)\n self.bn3 = nn.BatchNorm2d(out_channels)\n \n # Shuffle operation\n self.shuffle = ChannelShuffle(groups)\n \n # Shortcut connection if input and output channels are the same\n if in_channels == out_channels:\n self.shortcut = nn.Sequential()\n else:\n self.shortcut = nn.Sequential(\n nn.Conv2d(in_channels, out_channels, kernel_size=1, stride=1, padding=0, bias=False),\n nn.BatchNorm2d(out_channels)\n )\n \n def forward(self, x):\n \"\"\"\n Forward pass for ShuffleNet unit.\n\n :param x: Input tensor, shape (batch_size, in_channels, height, width)\n :return: Output tensor, shape (batch_size, out_channels, height, width)\n \"\"\"\n out = F.relu(self.bn1(self.conv1(x)))\n out = self.bn2(self.conv2(out))\n out = self.shuffle(out)\n out = F.relu(self.bn3(self.conv3(out)))\n \n out += self.shortcut(x)\n return out\n\nclass ChannelShuffle(nn.Module):\n def __init__(self, groups):\n \"\"\"\n Channel shuffle operation.\n\n :param groups: Number of groups for shuffling.\n \"\"\"\n super(ChannelShuffle, self).__init__()\n self.groups = groups\n \n def forward(self, x):\n \"\"\"\n Forward pass for channel shuffle.\n\n :param x: Input tensor, shape (batch_size, channels, height, width)\n :return: Output tensor, shape (batch_size, channels, height, width)\n \"\"\"\n batch_size, channels, height, width = x.size()\n channels_per_group = channels // self.groups\n \n # Reshape\n x = x.view(batch_size, self.groups, channels_per_group, height, width)\n \n # Transpose\n x = x.transpose(1, 2).contiguous()\n \n # Flatten\n x = x.view(batch_size, -1, height, width)\n \n return x\n \nbatch_size = 10\ninput_channels = 240\nout_channels = 480\ngroups = 3\nheight = 224\nwidth = 224\nnum_classes = 1000\n\ndef get_inputs():\n return [torch.rand(batch_size, input_channels, height, width)]\n\ndef get_init_inputs():\n return [input_channels, out_channels, groups]```\n"}, "L3_031": {"ctx": {"claude-opus-5-5": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier attention problems (wrong results or slower than eager)\n- Pitfall: Handle every optional forward argument (e.g. initial_states) and every intermediate the reference includes, even when it defaults to zeros. Verify the returned tensor is the same slice and quantity the reference returns.\n- Pitfall: Do not algebraically restructure the reference'...'s exact operation order and test against it before optimizing.", "claude-opus-4-8": "## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)\n\n### Lessons about this environment (from official checker verdicts and verified outcomes)\n- Checker rule: getattr needs a literal, non-private attribute name\n- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.\n- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.\n- Checker rule: forward modified its input tensors in place\n- Checker rule: do not define a class named Model (the reference); define ModelNew only\n- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.\n- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.\n- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include and ; torch/extension.h does not provide them.\n- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.)\n- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.)\n- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.\n\n### Pitfalls seen on earlier attention problems (wrong results or slower than eager)\n- Pitfall: Handle every optional forward argument (e.g. initial_states) and every intermediate the reference includes, even when it defaults to zeros. Verify the returned tensor is the same slice and quantity the reference returns.\n- Pitfall: Do not algebraically restructure the reference'...'s exact operation order and test against it before optimizing."}, "same_for_readers": true, "ctx_chars": 2425, "ctx_sha": "5c5e8811718de973", "names_self": false, "family": "attention", "level": 3, "name": "VisionAttention", "instruction": "KernelBench level 3 problem L3_031 (VisionAttention), op family: attention.\nWrite ModelNew, a faster drop-in replacement for this reference Model using your own GPU kernels:\n```python\nimport torch\nimport torch.nn as nn\nimport torch.nn.functional as F\n\nclass Model(nn.Module):\n def __init__(self, embed_dim, num_heads):\n \"\"\"\n Attention Block using Multihead Self-Attention.\n :param embed_dim: Embedding dimension (the number of channels)\n :param num_heads: Number of attention heads\n \"\"\"\n super(Model, self).__init__()\n self.attn = nn.MultiheadAttention(embed_dim, num_heads)\n self.norm = nn.LayerNorm(embed_dim)\n\n def forward(self, x):\n \"\"\"\n Forward pass of the AttentionBlock.\n :param x: Input tensor of shape (B, C, H, W)\n :return: Output tensor of the same shape (B, C, H, W)\n \"\"\"\n B, C, H, W = x.shape\n x = x.view(B, C, H * W).permute(2, 0, 1) # (seq_len, batch_size, embed_dim)\n attn_output, _ = self.attn(x, x, x)\n x = self.norm(attn_output + x) # (seq_len, batch_size, embed_dim)\n x = x.permute(1, 2, 0).view(B, C, H, W)\n return x\n\nembed_dim = 128\nnum_heads = 4\nbatch_size = 2\nnum_channels = embed_dim\nimage_height = 128\nimage_width = 128\n\ndef get_inputs():\n return [torch.rand(batch_size, num_channels, image_height, image_width)]\n\ndef get_init_inputs():\n return [embed_dim, num_heads]```\n"}}