## Kernel memory (items verified by the protected evaluator on training problems; may not all apply)

### Lessons about this environment (from official checker verdicts and verified outcomes)
- Pitfall: A reply without a ```python fenced code block was rejected by the checker. Always wrap the full ModelNew source in a ```python block.
- Checker rule: getattr needs a literal, non-private attribute name
- Pitfall: Output mismatch beyond 1e-4 occurred repeatedly. Fix by forcing exact fp32 tl.dot(allow_tf32=False) and exact masking: K bounds at block granularity, tril mask, and zero-initialized output for skipped tiles.
- Checker rule: forward modified its input tensors in place
- Checker rule: do not define a class named Model (the reference); define ModelNew only
- Process: never SUBMIT code that has not passed ACTION: CHECK in this episode. Untested submissions that fail to compile or mismatch the reference score 0; a CHECK costs one reply and shows the compiler output.
- Pitfall: cpp_sources is compiled by plain c++ without CUDA headers: never use cudaStream_t or at::cuda::getCurrentCUDAStream there. Put wrappers needing streams in cuda_sources, keeping only plain-type prototypes in cpp_sources.
- Pitfall: If cpp_sources must reference CUDA types or the current stream, explicitly #include <cuda_runtime.h> and <ATen/cuda/CUDAContext.h>; torch/extension.h does not provide them.
- Checker rule: assignment to attribute 'm.conv1' is not allowed (only self.<x>)
- Checker rule: assignment to attribute 'm.bn1' is not allowed (only self.<x>)
- Checker rule: assignment to attribute 'm.conv2' is not allowed (only self.<x>)
- Checker rule: assignment to attribute 'm.bn2' is not allowed (only self.<x>)
- Checker rule: assignment to attribute 'm.downsample' is not allowed (only self.<x>)
- Checker rule: At least one of your own kernels must actually launch during forward; a pure torch path (even with a compiled but unused kernel) is rejected as no_custom_kernel.

### Pitfalls seen on earlier conv problems (wrong results or slower than eager)
- Pitfall: Before hand-writing a dense conv, benchmark against cuDNN; a naive Triton or CUDA kernel rarely wins. Reserve custom kernels for fusing cheap elementwise ops around the conv.
- Pitfall: Don't write direct convolution as one output channel per program with scalar weight loads; each input pixel gets re-read per output channel. Tile over output channels and use tl.dot (implicit GEMM).
- Pitfall: Avoid per-element div/mod index decoding plus per-tap weight gathers in stencil kernels. Use a 2D/3D grid (plane, row-tile, col-tile) and load per-channel weights once per program.
- Pitfall: For depthwise conv, don'...'s 2D output plane, reuse input rows via shared memory or registers, and make kernel dims constexpr.
- Pitfall: Fuse post-conv elementwise/reduction ops with following pooling into one kernel instead of separate launches that write and re-read full-size intermediates. Unfused memory-bound epilogues after cuDNN conv easily end up slower than eager.
- Pitfall: For softmax or reduction over the channel dim of NC... tensors, avoid one program per spatial position with channel-strided loads. Tile a 2D [channels × contiguous spatial block] so loads coalesce along the innermost dimension.

### A verified kernel for a related conv problem (L2_069 Conv2d_HardSwish_ReLU, 1.25x): adapt what applies
```python
import torch
import torch.nn as nn
import torch.nn.functional as F
import triton
import triton.language as tl


@triton.jit
def act_kernel(x_ptr, out_ptr, TOTAL, BLOCK: tl.constexpr):
    pid = tl.program_id(0)
    offs = pid * BLOCK + tl.arange(0, BLOCK)
    mask = offs < TOTAL
    v = tl.load(x_ptr + offs, mask=mask, other=0.0)
    # hardswish: x * clamp(x+3,0,6)/6
    hs = v * tl.minimum(tl.maximum(v + 3.0, 0.0), 6.0) / 6.0
    r = tl.maximum(hs, 0.0)
    tl.store(out_ptr + offs, r, mask=mask)


class ModelNew(nn.Module):
    def __init__(self, in_channels, out_channels, kernel_size):
        super(ModelNew, self).__init__()
        self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)

    def forward(self, x):
        out = self.conv(x).contiguous()
        TOTAL = out.numel()
        res = torch.empty_like(out)
        BLOCK = 1024
        grid = (triton.cdiv(TOTAL, BLOCK),)
        act_kernel[grid](out, res, TOTAL, BLOCK=BLOCK)
        return res
```

### A verified kernel for a related conv problem (L2_025 Conv2d_Min_Tanh_Tanh, 1.01x): adapt what applies
```python
import torch
import torch.nn as nn
import torch.nn.functional as F
import triton
import triton.language as tl


@triton.jit
def min_tanh_kernel(x_ptr, out_ptr, C, S, NS, BLOCK: tl.constexpr):
    pid = tl.program_id(0)
    offs = pid * BLOCK + tl.arange(0, BLOCK)
    mask = offs < NS
    n = offs // S
    s = offs % S
    base = n.to(tl.int64) * C * S + s
    acc = tl.full((BLOCK,), 1e30, tl.float32)
    for c in range(C):
        v = tl.load(x_ptr + base + c * S, mask=mask, other=1e30)
        acc = tl.minimum(acc, v)
    acc = tl.minimum(tl.maximum(acc, -1e30), 1e30)
    t = tl.extra.cuda.libdevice.tanh(acc)
    t = tl.extra.cuda.libdevice.tanh(t)
    tl.store(out_ptr + offs, t, mask=mask)


class ModelNew(nn.Module):
    def __init__(self, in_channels, out_channels, kernel_size):
        super(ModelNew, self).__init__()
        self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)

    def forward(self, x):
        x = self.conv(x).contiguous()
        N, C, H, W = x.shape
        S = H * W
        out = torch.empty((N, 1, H, W), device=x.device, dtype=x.dtype)
        NS = N * S
        BLOCK = 1024
        grid = (triton.cdiv(NS, BLOCK),)
        min_tanh_kernel[grid](x, out, C, S, NS, BLOCK=BLOCK)
        return out
```